An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

    Corresponding author: Jihai Duan, drdjh98@163.com
  • Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology, Guilin 541004, China

Key words: SAR ADCdynamic latch comparatoroutput offset voltage storage technologykickback noise

Abstract: This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

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1.   Introduction
  • Analog to digital converters (ADCs) which are essential building blocks of many portable systems provide a bridge between the physical world and digital signal processing systems. High precision, high speed and low power consumption have always been the research focus of ADC design. Furthermore, a comparator is the most important part of an SAR (successive approximation register) ADC.

    SAR ADCs have many excellent characteristics such as a small circuit scale[1, 2], a low dynamic power consumption and a medium precision[3, 4]. A traditional SAR ADC has binary weighted capacitor arrays, which is difficult to obtain a lower power consumption and better match for high precision. The SAR ADC presented in Ref. [5] used a single-ended segmented architecture to reduce the number of capacitors. However, the precision was poor. The SAR ADC presented in Ref. [6] used a pre-amplifier latch static comparator, which had a high precision. However, the disadvantages were the low speed and high power consumption. The SAR ADC presented in Ref. [7] used a preamplifier latch dynamic comparator, which had a high speed Nevertheless, the comparator suffered from offset voltage and kickback noise.

    In order to overcome the problems mentioned above, this paper presents an 8-bit 1 MS/s SAR ADC, which uses the improved segmented capacitor DAC (digital to analog converter) structure to reduce the capacitance. Furthermore, the modified preamplifier latch dynamic comparator with offset voltage cancellation is used, which has high speed and high precision.

2.   Design of SAR ADC
  • The overall structure of the proposed SAR ADC is shown in Fig. 1, including a pair of differential sample-and-hold and DAC, a dynamic comparator and an SAR. It operates by the analog input signal compared with a list of reference voltages in turn, and then obtains the results of every bit. During every converter period, the comparator needs to complete 8 times of comparison with the feedback of the DAC and the SAR. The SAR requires the feedback signal of the comparator to get every bit.

    The differential segmented capacitor DAC is combined with the sample-and-hold circuit, operated by switches to control charge and discharge of the capacitor arrays. The modified preamplifier latch dynamic comparator with offset voltage cancellation consists of a preamplifier, a latch comparator, some coupling capacitors and switches. The successive approximation register which mainly consists of D flip-flops controls the timing sequence of the overall circuit. The conversion requires 10 clock periods: in the first period resetting, sampling and eliminating the offset of the comparator were done; eight periods (the second to the ninth period) are the successive approximation cycles, and results output in the last period.

  • 2.1.   Sample-and-hold and DAC capacitor arrays

  • The total power consumption of the charge redistribution DAC is proportional to the total capacitance and the switching frequency. The conventional capacitor arrays consume a large amount of power and occupy a large size, so a segmented capacitor DAC is adopted. Fig. 2 shows the architecture of the charge redistribution DAC, which consists of two differential segmented capacitor arrays and some switches controlled by the SAR. The unit capacitor in the DAC consists of a series of two capacitors. A differential DAC structure can suppress the common mode error and even-order harmonics caused by a single-ended structure. The $V_{\rm ref}$ is the reference voltage for comparison, the $V_{\rm in+}$ and $V_{\rm in-}$ are differential inputs, the $D_{7}$-$D_0$ and $D_{\rm N7}$-$D_{\rm N0} $ from the SAR control the switches of the DAC.

    The voltages of $V_{\rm dp}$ and $V_{\rm dn}$ depend on the SAR at the charge redistribution phase, which can be represented as

    where $V_{\rm in+}$ and $V_{\rm in-}$ are voltages of the differential input, $V_{\rm CM}$ is the common mode voltage, $V_{\rm ref}$ is the reference voltage, $D_{ i}$ or $D_{{\rm N}i}$ is the switching signal from the SAR, and $ i = 0$, 1, 2, ..., 7.

    The unit capacitance is obtained by the standard deviation of DNL and the mismatch of MIM (metal-insulator-metal) capacitor in SMIC 0.18 $\mu $m CMOS technology. According to the maximum standard deviation of DNL for a segmented N-bit DAC with M-bit MSB (most significant bit), the relations between Sigma($C_{\rm UT})$ (the standard deviation of unit capacitance $C_{\rm UT})$ and $C_{\rm UT}$ can be expressed as

    According to the mismatch documents of SMIC 0.18 $\mu $m CMOS technology, the Sigma($C_{\rm UT}) $ can be given by

    else,

    where slope is the match factor, $A$ is the area of unit capacitor $C_{\rm UT}$, and the density of capacitor $ K_{\rm C} $ is about 1 fF/$\mu$m$^{\mathrm{2}}$. From Eqs. (3)-(5), the unit capacitor $C_{\rm UT}$ can be expressed as

    For the presented DAC fabricated with SMIC 0.18 $\mu$m CMOS technology, the capacitance of $C_{\rm UT}$ is larger than 7.65 fF. The capacitance $C_{\rm U}$ (in Fig. 2) is chosen as 10.15 × 10.15 $\mu$m$^{\mathrm{2}}$ (100 fF), which is enough for 0.1% matching according to the report provided by the foundry. In order to reduce the size and power consumption of capacitors in DAC capacitor array, $C_{\rm UT}$ (50 fF) is obtained by two $C_{\rm U}$ in series. The total capacitance is 4.4 pF for the proposed SAR ADC and 6.4 pF for a conventional differential segmented DAC Therefore, the proposed differential DAC can reduce the chip size and power consumption significantly.

  • 2.2.   Design of comparator

  • In an SAR ADC, a comparator can achieve a quantization process to digital output signals from analog signals. The noise and the offset voltage affect the performance of the SAR ADC. However, this offset voltage depending on the dimensions of the transistors cannot be reduced only by increasing the sizes of the transistors. In this design, the modified preamplifier latch dynamic comparator with the output offset storage technology is adopted. The proposed comparator consisting of a preamplifier, a latch comparator and an output stage is shown in Fig. 3.

    During the offset voltage storage period, the switches $S_{1}$-$S_{4}$ are closed, $V_{\rm i+}$ and $V_{\rm i-} $ are shorted, and the offset voltages are stored on the capacitors $C_{1}$ and $C_{2}$. During the conversion period, the new offset voltages are canalled with the previous stored offset voltages. The modified preamplifier is improved by a cascode amplifier, two clamping diodes and a clock switch, as shown in Fig. 4. $V_{\rm b1}$ and $V_{\rm b2}$ are the bias voltages, and the CLK is a clock signal. When the CLK is low, the preamplifier does not work. The input signal $V_{\rm i+}$ and $V_{\rm i-}$ will be amplified when the CLK jumps high. The Cascode amplifier with crossing coupling load is used to obtain a high gain. Moreover, the two clamping diodes restrict the voltage difference swing between $V_{\rm pp}$ and $V_{\rm pn}$, which can improve the speed of the comparator. The gain $A_{\rm v} $ of the preamplifier is given as

    where $g_{\rm mi}$ is the transconductance of transistor M$_{\rm i}$, $r_{\rm oi}$ is the resistance between the leakage and the source of transistor M$_{\rm i}$.

    Besides the offset voltage, the latch also introduces kickback noise that will degrade the precision of the SAR ADC. The charge and discharge time of the crossing coupling structure restrict the speed of the dynamic comparator. Compared with the conventional structure[8], a pair of crossing couplings structure consisting of N$_3$ and N$_4$, two pairs of CMOS switches consisting of N$_9$-N$_{12}$, a pair of positive feedback structures consisting of N$_7$ and N$_8$, and a pair of reset structures consisting of N$_5$ and N$_6$ are added, as shown in Fig. 5.

    At the phase of comparison, N$_1$, N$_2$ and N$_9$-N$_{14}$ turn on, N$_5$, N$_6$ and N$_{17}$-N$_{20}$ turn off. von will discharge through the branch consisting of N$_1$, N$_9$, N$_{10}$ and N$_{13}$, meanwhile, vop will discharge through another branch consisting of N$_2$, N$_{11}$, N$_{12}$ and N$_{14}$. The voltages of outn and outp will increase. When outn or outp is higher than $V_{\rm th} $ (threshold voltage), N$_{7}$ or N$_{8}$ will turn on, which adds an extra discharge branch and plays the role as a positive feedback; if $V_{\rm A}$ or $V_{\rm B}$ is higher than $V_{\rm th}$, N$_3$ or N$_{4}$ would turn on, which provide an extra discharge branch, too. Fig. 6 shows a simplified model of the latch comparator. The time constant can be written as

    where $C$ is the equivalent capacitance at output, and $g_{\rm m14}$ is transconductance of N$_{14}$. Most of $C$ is the capacitance between gate and source, $\tau_{L} $can be expressed by

    where $K_{14}' =\mu_{n} C_{\rm ox} $, $W_{14}$ is the width of N$_{14}$, $L_{14}$ is the length of N$_{14}$, and $I$ is the drain-source current of N$_{14}$. The delay time can be written as

    where $v_{\rm IN}=v_{\rm pp}-v_{\rm pn}$, $V_{\rm OH}$ is output high level, and $V_{\rm OL}$ is output low level. The delay time depends on $I $ and $v_{\rm IN}$, and for a conventional latch comparison, $I_{\rm conv}$ can be represented by

    where $i_{\rm d2}$ is the drain-source current of N$_2$, so the delay time for a conventional latch comparator is very long. $i_{\rm a}$ and $i_{\rm b}$ in Fig. 6 can be expressed as

    The current $ I $ is increased to $i_{\rm a}$ or $i_{\rm b}$, so the delay time of the modified latch comparator is short. Fig. 7 shows the delay time of the proposed latch compared with the conventional design[8]. The delay time is 59.2 ps for the modified latch comparator. However, it was 516.8 ps for the conventional structure[8]. Therefore, N$_3$, N$_4$, N$_7$ and N$_8$ can improve the speed of the comparator significantly.

    In the traditional structure without N$_3$-N$_{12}$, the node voltages $V_{\rm A}$ and $V_{\rm B}$ are both pushed to VDD at the phase of reset. Furthermore, one of them will be pulled to GND after regeneration is completed. Therefore, the kickback noise affects the performance of the comparator seriously. Fig. 8 shows a simplified model of the proposed latch comparator. The CMOS switches isolate the input stage from the regenerative inverter pair. During the latch reset phase, $V_{\rm A}$ and $V_{\rm B}$ are 0 V. After the comparison is completed, $V_{\rm A}$ and $V_{\rm B}$ are still 0 V. The voltage variations at the drains of the input pair are much less than the traditional design, so it can reduce the kickback noise. Fig. 9 shows the simulation results of kickback noise at the latch input. For the conventional structure[8], the amplitude of kickback noise is 56 mV. However, the noise amplitude is 3 mV for the proposed latch. Therefore, the proposed latch reduces kickback noise significantly.

    The transient response of the proposed comparator is shown in Fig. 10. The simulated results show the resolution is less than 500 $\mu$V with a 100 MHz clock and 1.8 V power supply. Therefore, the modified latch comparator can achieve higher speed and precision.

  • 2.3.   Chip implementation

  • A die photo of the realized SAR ADC in 0.18 $\mu$m CMOS is shown in Fig. 11. The core occupies 320 × 345 $\mu$m$^{\mathrm{2}}$, while the remaining area in the figure is occupied by ESDs and PADs. In order to reduce the chip area, a serializer is used.

3.   Measurement results
  • The DNL and INL of the SAR ADC are measured with code density using a full-swing differential sinusoidal signal with amplitude of 1.8 V. Figs. 12 and 13 show the measurement results of the INL (integral nonlinearity) and DNL (differential nonlinearity) at 1 MS/s sampling frequency. The peak INL and DNL are $+$0.86/$-$1.1 LSB and $+$0.82/$-$0.64 LSB. The |INL| is larger than 1 LSB because of capacitors' mismatch of manufacturing technique or layout design.

    The spectrum at 1 MS/s for a differential full-scale sinusoidal input with amplitude of 1.8 V is shown in Fig. 14. The SNDR is 48.29 dB (ENOB $=$ 7.72 bits), and the $\textit{SFDR}$ is 61.8 dB with 67.5 $\mu $W power consumption at input frequency 499.02 kHz. Fig. 15 shows the variation of the SNDR and SFDR with respect to frequency. The overall ADC performance comparison is listed in Table 1. Compared to the ADCs in Table 1, this design achieves the best ENOB (SNDR) and SFDR with higher sampling frequency and lower power consumption.

4.   Conclusion
  • In this work, a low-power high ENOB (SNDR) 8-bit SAR ADC with 1 MS/s sampling frequency is presented. By using the improved differential segmented DAC and the improved low kickback noise dynamic comparator, the proposed SAR ADC achieved an ENOB of 7.72 bits and an SFDR of 61.8 dB with lower power and smaller capacitance

Figure (15)  Table (1) Reference (13) Relative (20)

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