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Volume 26, Issue 11, Nov 2005
LETTERS
AlGaN/GaN High Electron Mobility Transistors on Sapphires with fmax of 100GHz
Li Xianjie, Zeng Qingming, Zhou Zhou, Liu Yugui, Qiao Shuyun, Cai Daomin, Zhao Yonglin, Cai Shujun
Chin. J. Semicond.  2005, 26(11): 2049-2052
Abstract PDF

AlGaN/GaN high electron mobility transistors grown on sapphire substrates with a 0.3μm gate length and 100μm gate width are fabricated.The device reveals a drain current saturation density of 0.85A/mm at a gate voltage of 0V and a peak transconductance of 225mS/mm.The unity current gain cutoff frequency and maximum frequency of oscillation are obtained as 45 and 100GHz,respectively.The output power density and gain are 1.8W/mm and 9.5dB at 4GHz,and 1.12W/mm and 11.5dB at 8GHz.

AlGaN/GaN high electron mobility transistors grown on sapphire substrates with a 0.3μm gate length and 100μm gate width are fabricated.The device reveals a drain current saturation density of 0.85A/mm at a gate voltage of 0V and a peak transconductance of 225mS/mm.The unity current gain cutoff frequency and maximum frequency of oscillation are obtained as 45 and 100GHz,respectively.The output power density and gain are 1.8W/mm and 9.5dB at 4GHz,and 1.12W/mm and 11.5dB at 8GHz.
A Wavelength Tunable DBR Laser Integrated with an Electro-Absorption Modulator by a Combined Method of SAG and QWI
Zhang Jing, Li Baoxia, Zhao Lingjuan, Wang Baojun, Zhou Fan, Zhu Hongliang, Bian Jing, Wang Wei
Chin. J. Semicond.  2005, 26(11): 2053-2057
Abstract PDF

We report a wavelength tunable electro-absorption modulated DBR laser based on a combined method of SAG and QWI.The threshold current is 37mA and the output power at 100mA gain current is 3.5mW.When coupled to a single-mode fiber with a coupling efficiency of 15%,more than a 20dB extinction ratio is observed over the change of EAM bias from 0 to -2V.The 4.4nm continuous wavelength tuning range covers 6 channels on a 100GHz grid for WDM telecommunications.

We report a wavelength tunable electro-absorption modulated DBR laser based on a combined method of SAG and QWI.The threshold current is 37mA and the output power at 100mA gain current is 3.5mW.When coupled to a single-mode fiber with a coupling efficiency of 15%,more than a 20dB extinction ratio is observed over the change of EAM bias from 0 to -2V.The 4.4nm continuous wavelength tuning range covers 6 channels on a 100GHz grid for WDM telecommunications.
Lumped Equivalent Circuit of Planar Spiral Inductor for CMOS RFIC Application
Zhao Jixiang
Chin. J. Semicond.  2005, 26(11): 2058-2061
Abstract PDF

A lumped π-type equivalent circuit of planar spiral inductor for CMOS RFIC application is developed by the domain decomposition method for conformal modules (DDM-CM).Closed form expressions of lumped parameters for a square spiral inductor on a Si-SiO2 substrate are obtained and verified with the previously published experimental results.

A lumped π-type equivalent circuit of planar spiral inductor for CMOS RFIC application is developed by the domain decomposition method for conformal modules (DDM-CM).Closed form expressions of lumped parameters for a square spiral inductor on a Si-SiO2 substrate are obtained and verified with the previously published experimental results.
An Efficient Test Data Compression Technique Based on Codes
Fang Jianping, Hao Yue, Liu Hongxia, Li Kang
Chin. J. Semicond.  2005, 26(11): 2062-2068
Abstract PDF

This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes.The method makes a full analysis of the factors which influence test parameters:compression ratio,test application time,and area overhead.To improve the compression ratio,the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step.With a novel on-chip decoder,low test application time and low area overhead are obtained by hybrid run length codes.Finally,an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method.

This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes.The method makes a full analysis of the factors which influence test parameters:compression ratio,test application time,and area overhead.To improve the compression ratio,the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step.With a novel on-chip decoder,low test application time and low area overhead are obtained by hybrid run length codes.Finally,an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method.
PAPERS
Effects of Thickness on Properties of ZnO Films Grown on Si by MOCVD
Shen Wenjuan, Wang Jun, Duan Yao, Wang Qiyuan, Zeng Yiping
Chin. J. Semicond.  2005, 26(11): 2069-2073
Abstract PDF

High quality ZnO films are successfully grown on Si(100) substrates by metal-organic chemical vapor deposition at 300℃.The effects of the thickness of the ZnO films on crystal structure,surface morphology,and optical properties are investigated using X-ray diffraction,scanning probe microscopy,and photoluminescence spectra,respectively.It is shown that the ZnO films grown on Si substrates have a highly-preferential C-axis orientation,but it is difficult to obtain the better structural and optical properties of the ZnO films with the increasing of thickness.It is maybe due to that the grain size and the growth model are changed in the growth process.

High quality ZnO films are successfully grown on Si(100) substrates by metal-organic chemical vapor deposition at 300℃.The effects of the thickness of the ZnO films on crystal structure,surface morphology,and optical properties are investigated using X-ray diffraction,scanning probe microscopy,and photoluminescence spectra,respectively.It is shown that the ZnO films grown on Si substrates have a highly-preferential C-axis orientation,but it is difficult to obtain the better structural and optical properties of the ZnO films with the increasing of thickness.It is maybe due to that the grain size and the growth model are changed in the growth process.
Growth of Space Ordered 1.3μm InAs Quantum Dots on GaAs(100) Vicinal Substrates by MOCVD
Liang Song, Zhu Hongliang, Pan Jiaoqing, Wang Wei
Chin. J. Semicond.  2005, 26(11): 2074-2079
Abstract PDF

Space ordered 1.3μm self-assembled InAs QDs are grown on GaAs(100) vicinal substrates by MOCVD.Photoluminescence measurements show that the dots on vicinal substrates have a much higher PL intensity and a narrower FWHM than those of dots on exact substrates, which indicates better material quality.To obtain 1.3μm emissions of InAs QDs,the role of the so called InGaAs strain cap layer (SCL) and the strain buffer layer (SBL) in the strain relaxation process in quantum dots is studied.While the use of SBL results only in a small change of emission wavelength,SCL can extend the QD’s emission over 1.3μm due to the effective strain reducing effect of SCL.

Space ordered 1.3μm self-assembled InAs QDs are grown on GaAs(100) vicinal substrates by MOCVD.Photoluminescence measurements show that the dots on vicinal substrates have a much higher PL intensity and a narrower FWHM than those of dots on exact substrates, which indicates better material quality.To obtain 1.3μm emissions of InAs QDs,the role of the so called InGaAs strain cap layer (SCL) and the strain buffer layer (SBL) in the strain relaxation process in quantum dots is studied.While the use of SBL results only in a small change of emission wavelength,SCL can extend the QD’s emission over 1.3μm due to the effective strain reducing effect of SCL.
Characteristics of a 0.1μm SOI Grooved Gate pMOSFET
Shao Hongxu, Sun Baogang, Wu Junfeng, Zhong Xinghua
Chin. J. Semicond.  2005, 26(11): 2080-2084
Abstract PDF

A 0.1μm SOI grooved gate pMOSFET with 5.6nm gate oxide is fabricated and demonstrated.The groove depth is 180nm.The transfer characteristics and the output characteristics are shown.At Vds=-1.5V,the drain saturation current is 380μA and the off-state leakage current is 1.9nA;the sub-threshold slope is 115mV/dec at Vds=-0.1V and DIBL factor is 70.7mV/V.The electrical characteristic comparison between the 0.1μm SOI grooved-gate pMOSFET and the 0.1μm bulk grooved gate one with the same process demonstrates that a 0.1μm SOI grooved gate pMOSFET has better characteristics in current-driving capability and sub-threshold slope.

A 0.1μm SOI grooved gate pMOSFET with 5.6nm gate oxide is fabricated and demonstrated.The groove depth is 180nm.The transfer characteristics and the output characteristics are shown.At Vds=-1.5V,the drain saturation current is 380μA and the off-state leakage current is 1.9nA;the sub-threshold slope is 115mV/dec at Vds=-0.1V and DIBL factor is 70.7mV/V.The electrical characteristic comparison between the 0.1μm SOI grooved-gate pMOSFET and the 0.1μm bulk grooved gate one with the same process demonstrates that a 0.1μm SOI grooved gate pMOSFET has better characteristics in current-driving capability and sub-threshold slope.
A Fractional-N CMOS DPLL with Self-Calibration
Liu Sujuan, Yang Weiming, Chen Jianxin, Cai Liming, Xu Dongsheng
Chin. J. Semicond.  2005, 26(11): 2085-2091
Abstract PDF

A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented.The self-calibration technique is employed to acquire wide lock range,low jitter,and fast acquisition.The DPLL works from 60 to 600MHz at a supply voltage of 1.8V.It also features a fractional-N synthesizer with digital 2nd-order sigma-delta noise shaping,which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum.The DPLL has been implemented in SMIC 0.18μm 1.8V 1P6M CMOS technology.The peak-to-peak jitter is less than 0.8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.

A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented.The self-calibration technique is employed to acquire wide lock range,low jitter,and fast acquisition.The DPLL works from 60 to 600MHz at a supply voltage of 1.8V.It also features a fractional-N synthesizer with digital 2nd-order sigma-delta noise shaping,which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum.The DPLL has been implemented in SMIC 0.18μm 1.8V 1P6M CMOS technology.The peak-to-peak jitter is less than 0.8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
Infrared Absorption of Spatially Ordered Quantum Dot Superlattices
Sun Yongwei, Ma Wenquan, Yang Xiaojie, Qu Yuhua, Hou Shihua, Jiang Desheng, Sun Baoquan, Chen Lianghui
Chin. J. Semicond.  2005, 26(11): 2092-2096
Abstract PDF

A self-organized InGaAs/GaAs quantum dot superlattice structure with three dimensionally spatial ordering is grown at 540℃ by molecular beam epitaxy.A Fourier transform infrared (FTIR) spectroscopy measurement demonstrates a distinct intersubband transition absorption peak with the wavelength centered at 11μm under the normal incidence geometry.As a comparison,the FTIR measurement shows that the same structure grown at 480℃ does not have normal incidence intersubband transition absorption.High resolution X-ray diffraction measurements indicate that the quantum dot superlattice grown at high temperatures has a better crystalline quality than that grown at low temperatures.Atomic force microscopy measurements reveal that the quantum dots grown at 540℃ show clear lateral ordering,while those grown at 480℃ show a lack of lateral ordering.In order to remove the interference effect under the normal incidence geometry,the normal incidence absorption measurement is proposed, using the structure with the same growth condition but without doping the quantum dot layers.The accuracy and the resolution of the measurement under normal incidence geometry are therefore enhanced.Our results indicate that the quantum dot superlattice structure with spatial ordering is more suitable to be utilized in the infrared photodetector than the structure without spatial ordering.

A self-organized InGaAs/GaAs quantum dot superlattice structure with three dimensionally spatial ordering is grown at 540℃ by molecular beam epitaxy.A Fourier transform infrared (FTIR) spectroscopy measurement demonstrates a distinct intersubband transition absorption peak with the wavelength centered at 11μm under the normal incidence geometry.As a comparison,the FTIR measurement shows that the same structure grown at 480℃ does not have normal incidence intersubband transition absorption.High resolution X-ray diffraction measurements indicate that the quantum dot superlattice grown at high temperatures has a better crystalline quality than that grown at low temperatures.Atomic force microscopy measurements reveal that the quantum dots grown at 540℃ show clear lateral ordering,while those grown at 480℃ show a lack of lateral ordering.In order to remove the interference effect under the normal incidence geometry,the normal incidence absorption measurement is proposed, using the structure with the same growth condition but without doping the quantum dot layers.The accuracy and the resolution of the measurement under normal incidence geometry are therefore enhanced.Our results indicate that the quantum dot superlattice structure with spatial ordering is more suitable to be utilized in the infrared photodetector than the structure without spatial ordering.
Small Amplitude Approximation and Dynamic Stabilities of a Strained Superlattice
Luo Shiyu, Shao Mingzhu
Chin. J. Semicond.  2005, 26(11): 2097-2101
Abstract PDF

Effect of the Surface of HgCdTe Epilayers on Infrared Transmission Spectra
Zhang Xiaolei, Kong Jincheng, Ma Qinghua, Wu Jun, Yang Yu, Ji Rongbin
Chin. J. Semicond.  2005, 26(11): 2102-2106
Abstract PDF

Infrared transmission spectra of liquid phase expitaxial Hg1-xCdxTe films are measured with a FTIR spectrometer.It is found that the as-grown Hg1-xCdxTe films have a declining absorption edge and a low transmission rate in intrinsic absorption spectra. Hg1-xCdxTe films are etched and the effects of etching are analyzed by SEM,electron probe analyzer,and surface profiler.These measurements indicate that the differences in concentration of mercury and surface flatness of Hg1-xCdxTe film surfaces result in differences in infrared transmission spectra.Band-band tail transition theories and surface scattering mechanism are used to interpret the phenomenon.

Infrared transmission spectra of liquid phase expitaxial Hg1-xCdxTe films are measured with a FTIR spectrometer.It is found that the as-grown Hg1-xCdxTe films have a declining absorption edge and a low transmission rate in intrinsic absorption spectra. Hg1-xCdxTe films are etched and the effects of etching are analyzed by SEM,electron probe analyzer,and surface profiler.These measurements indicate that the differences in concentration of mercury and surface flatness of Hg1-xCdxTe film surfaces result in differences in infrared transmission spectra.Band-band tail transition theories and surface scattering mechanism are used to interpret the phenomenon.
Effects of Germanium on Oxygen Precipitation in Heavily Boron-Doped Czochralski Silicon
Jiang Huihua, Yang Deren, Tian Daxi, Ma Xiangyang, Li Liben, Que Duanlin
Chin. J. Semicond.  2005, 26(11): 2107-2110
Abstract PDF

Oxygen precipitation in conventional heavily B-doped Czochralski (CZ) silicon (HB-Si) and heavily Ge-B codoped CZ silicon (Ge codoped HB-Si) subjected to single step annealing at 650~1150℃ for 64h or low-high two step annealing(650℃/16h+1000℃/16h and 800℃/4~128h+1000℃/16h) are comparatively investigated.It is found that the density of bulk microdefects (BMDs) in Ge codoped HB-Si is much lower than that in HB-Si.The mechanism of which is preliminarily discussed.

Oxygen precipitation in conventional heavily B-doped Czochralski (CZ) silicon (HB-Si) and heavily Ge-B codoped CZ silicon (Ge codoped HB-Si) subjected to single step annealing at 650~1150℃ for 64h or low-high two step annealing(650℃/16h+1000℃/16h and 800℃/4~128h+1000℃/16h) are comparatively investigated.It is found that the density of bulk microdefects (BMDs) in Ge codoped HB-Si is much lower than that in HB-Si.The mechanism of which is preliminarily discussed.
Application of a SiGe Multi-Quantum Well Grown by UHV-CVDfor Thermophotovoltaic Cells
Sun Weifeng, Ye Zhizhen, Zhu Liping, Zhao Binghui
Chin. J. Semicond.  2005, 26(11): 2111-2114
Abstract PDF

To verify the direct-gap transition of a SiGe multi-quantum well and grope for its application in thermophotovoltaic cells,a high quality SiGe multi-quantum well is grown by our UHV-CVDII system.The absorption measurement of the SiGe multi-quantum well by multiple internal reflection indicates that the extension of the absorption is up to 1450nm and transition probability caused by the quantum effect in the quantum well of strained SiGe thin layer is higher.Consequently,the absorption efficiency of thermophotovoltaic cells will be increased significantly.

To verify the direct-gap transition of a SiGe multi-quantum well and grope for its application in thermophotovoltaic cells,a high quality SiGe multi-quantum well is grown by our UHV-CVDII system.The absorption measurement of the SiGe multi-quantum well by multiple internal reflection indicates that the extension of the absorption is up to 1450nm and transition probability caused by the quantum effect in the quantum well of strained SiGe thin layer is higher.Consequently,the absorption efficiency of thermophotovoltaic cells will be increased significantly.
Piezoresistive Effect of Polysilicon Films at High Temperature
Huo Mingxue, Liu Xiaowei, Zhang Dan, Wang Xilian, Song Minghao
Chin. J. Semicond.  2005, 26(11): 2115-2119
Abstract PDF

The high-temperature piezoresistive effect of polysilicon films is investigated.The relation between gauge factors of heavy doped polysilicon films deposited by LPCVD and temperatures is researched and attained,considering experimental influences of deposition temperature and film thickness on gauge factors.Polysilicon films with a Boron-doped concentration of about 1e19cm-3 are experimentally studied from room temperature to 560℃.Experimental results show that the polysilicon piezoresistors can work over 560℃.

The high-temperature piezoresistive effect of polysilicon films is investigated.The relation between gauge factors of heavy doped polysilicon films deposited by LPCVD and temperatures is researched and attained,considering experimental influences of deposition temperature and film thickness on gauge factors.Polysilicon films with a Boron-doped concentration of about 1e19cm-3 are experimentally studied from room temperature to 560℃.Experimental results show that the polysilicon piezoresistors can work over 560℃.
Mathematical Morphology Based Algorithm to Measure Quantum Dots from AFM Photos
Jin Feng, Lu Huaxiang, Li Kai, Chen Yonghai, Wang Zhanguo
Chin. J. Semicond.  2005, 26(11): 2120-2126
Abstract PDF

This paper proposes an algorithm to obtain the statistic data of quantum dots from atomic force microscopy photos.Starting from identifying the dynamic values of each regional maximum,the peak of each qualified quantum dot is located.Their positions are used as the markers for the next step, which is to apply the marker watershed transform to obtain a rough segmentation of the quantum dots.According to the boundary of the coarse partition,each quantum dot is cut from the original photo.A process is then carried out to filter the possible attached substrates based on the area-height distribution of the current quantum dot.After all the above stages,all the quantum dots can be accurately and robustly extracted and thus their properties, such as height,lateral size,and volume,can easily be measured.

This paper proposes an algorithm to obtain the statistic data of quantum dots from atomic force microscopy photos.Starting from identifying the dynamic values of each regional maximum,the peak of each qualified quantum dot is located.Their positions are used as the markers for the next step, which is to apply the marker watershed transform to obtain a rough segmentation of the quantum dots.According to the boundary of the coarse partition,each quantum dot is cut from the original photo.A process is then carried out to filter the possible attached substrates based on the area-height distribution of the current quantum dot.After all the above stages,all the quantum dots can be accurately and robustly extracted and thus their properties, such as height,lateral size,and volume,can easily be measured.
Solution Growth of Morphology Controllable ZnO One-Dimensional Nanorods and Microrods
Zhang Linli, Guo Changxin, Chen Jiangang, Hu Juntao
Chin. J. Semicond.  2005, 26(11): 2127-2132
Abstract PDF

Various morphologies and different sized ZnO nanorods and microrods are synthesized onto glass substrates through a low-temperature,environmental benign,solution-based growth method by the source of zinc acetate and catalysts of hexamethylene tetramine or triethanolamine.The influence of the pH values and the concentration on the morphology of as-grown ZnO rods is discussed and the growth habits is analyzed.With increasing the concentration,the ratio of length to diameter gets small and the distribution of ZnO rods on the glass substrate changes from out of order to distribution along the growth axis c.When the pH value is from weak acid to weak alkali,the shape of ZnO samples gets from the long column to short one-pair rods grown symmetrically from one center to both sides.With the pH values further increasing,it can be grain.Regular hexagonal ZnO rods arrays can be fabricated by the control of certain pH and concentration of the solution.XRD,SEM, and PL are used to analyze the structure,morphology, and optical properties.The PL spectrum of the regular hexagonal ZnO rods shows that there is a broad green band with a peak at 530nm and a FWHM of 220nm.The green emission is attributed to the recombination of an electron in Vo+ to a hole in VB.

Various morphologies and different sized ZnO nanorods and microrods are synthesized onto glass substrates through a low-temperature,environmental benign,solution-based growth method by the source of zinc acetate and catalysts of hexamethylene tetramine or triethanolamine.The influence of the pH values and the concentration on the morphology of as-grown ZnO rods is discussed and the growth habits is analyzed.With increasing the concentration,the ratio of length to diameter gets small and the distribution of ZnO rods on the glass substrate changes from out of order to distribution along the growth axis c.When the pH value is from weak acid to weak alkali,the shape of ZnO samples gets from the long column to short one-pair rods grown symmetrically from one center to both sides.With the pH values further increasing,it can be grain.Regular hexagonal ZnO rods arrays can be fabricated by the control of certain pH and concentration of the solution.XRD,SEM, and PL are used to analyze the structure,morphology, and optical properties.The PL spectrum of the regular hexagonal ZnO rods shows that there is a broad green band with a peak at 530nm and a FWHM of 220nm.The green emission is attributed to the recombination of an electron in Vo+ to a hole in VB.
Preparation of Molybdenum-Doped Indium Oxide Thin Films by Channel Spark Ablation
Huang Li, Li Xifeng, Zhang Qun, Miao Weina, Zhang Li, Zhang Zhuangjian, Hua Zhongyi
Chin. J. Semicond.  2005, 26(11): 2133-2138
Abstract PDF

Molybdenum-doped indium oxide In2O3∶Mo (IMO) thin films are deposited on common glass substrates by channel spark ablation.The effect of oxygen pressure during the ablation on the optoelectrical properties of the films is studied.For the IMO films deposited at the substrate temperature Ts=350℃,the resistivity changes concavely while the carrier concentration varies convexly with the increase of oxygen pressure.The lowest resistivity and the carrier concentration reach 4.8e-4Ω·cm and 7.1e20cm-3,respectively.The mobility can reach to as high as 49.6cm2/(V·s) .The average transmittance in the visible region is more than 87% for all the samples.The work function of the IMO is 4.6eV measured by ultraviolet photoelectron spectroscopy.The X-ray diffraction diagram indicates that the as-grown IMO films are well crystallized with a preferred orientation of (222).The roughness evaluated by Rrms,Ra, and Rp-v measured by AFM are 0.72,0.44, and 15.4nm,respectively.

Molybdenum-doped indium oxide In2O3∶Mo (IMO) thin films are deposited on common glass substrates by channel spark ablation.The effect of oxygen pressure during the ablation on the optoelectrical properties of the films is studied.For the IMO films deposited at the substrate temperature Ts=350℃,the resistivity changes concavely while the carrier concentration varies convexly with the increase of oxygen pressure.The lowest resistivity and the carrier concentration reach 4.8e-4Ω·cm and 7.1e20cm-3,respectively.The mobility can reach to as high as 49.6cm2/(V·s) .The average transmittance in the visible region is more than 87% for all the samples.The work function of the IMO is 4.6eV measured by ultraviolet photoelectron spectroscopy.The X-ray diffraction diagram indicates that the as-grown IMO films are well crystallized with a preferred orientation of (222).The roughness evaluated by Rrms,Ra, and Rp-v measured by AFM are 0.72,0.44, and 15.4nm,respectively.
UHV/CVD Grown Strain Relaxed SiGe Buffer Layers for Strained Silicon
Wu Guibin, Ye Zhizhen, Liu Guojun, Zhao Binghui, Cui Jifeng
Chin. J. Semicond.  2005, 26(11): 2139-2142
Abstract PDF

Multi SiGe/Si layers with increasing Ge content are grown using ultra high vacuum chemical vapor deposition.Relaxation and Ge content are investigated with high resolution X-ray diffraction,SIMS,and AFM.By adopting this structure the Ge contents are remarkably improved,and a thin strain-relaxed SiGe buffer layer with high quality,low dislocation density,and smooth morphology is realized.The density of dislocations is calculated to be 1e6cm-2 through optical microscopy.

Multi SiGe/Si layers with increasing Ge content are grown using ultra high vacuum chemical vapor deposition.Relaxation and Ge content are investigated with high resolution X-ray diffraction,SIMS,and AFM.By adopting this structure the Ge contents are remarkably improved,and a thin strain-relaxed SiGe buffer layer with high quality,low dislocation density,and smooth morphology is realized.The density of dislocations is calculated to be 1e6cm-2 through optical microscopy.
Hot Electron Tunneling Mechanism of Current Collapse in GaN HFET
Xue Fangshi
Chin. J. Semicond.  2005, 26(11): 2143-2148
Abstract PDF

Two electron transition processes between channel and surface states in GaN HFET:hot electron tunneling and surface to band edge transition are investigated.Based on the tunneling between channel hot electrons and surface states,a new microscope mechanism of current collapse is proposed.Various experimental behaviors of photoionization spectroscopy,DLTS,transient current, and current collapse are explained by this microscopic mechanism.The different current collapse behaviors are investigated for various heterostructures,from which the optimized design of GaN HFET without current collapse is discussed.

Two electron transition processes between channel and surface states in GaN HFET:hot electron tunneling and surface to band edge transition are investigated.Based on the tunneling between channel hot electrons and surface states,a new microscope mechanism of current collapse is proposed.Various experimental behaviors of photoionization spectroscopy,DLTS,transient current, and current collapse are explained by this microscopic mechanism.The different current collapse behaviors are investigated for various heterostructures,from which the optimized design of GaN HFET without current collapse is discussed.
A Breakdown Voltage Model of a PSOI Structure with a p-Type Buried Layer
Duan Baoxing, Zhang Bo, Li Zhaoji
Chin. J. Semicond.  2005, 26(11): 2149-2153
Abstract PDF

A new PSOI structure with a p-type buried layer is developed,which is called BPSOI.Its mechanism of breakdown is an additive electric field modulation,which inducts new electric field peaks in surface electric field distribution by p-type buried layer charges.The on-resistance is decreased as a result of increasing drift region doping which is due to the neutralism of the p-type buried layer.The result is that the breakdown voltage is increased by 52%~58% and the on-resistance is decreased by 45%~48% in virtue of the 2D MEDICI simulation.

A new PSOI structure with a p-type buried layer is developed,which is called BPSOI.Its mechanism of breakdown is an additive electric field modulation,which inducts new electric field peaks in surface electric field distribution by p-type buried layer charges.The on-resistance is decreased as a result of increasing drift region doping which is due to the neutralism of the p-type buried layer.The result is that the breakdown voltage is increased by 52%~58% and the on-resistance is decreased by 45%~48% in virtue of the 2D MEDICI simulation.
A Novel Structure and Its Breakdown Mechanism of a SOI High Voltage Device with a Shielding Trench
Luo Xiaorong, Li Zhaoji, Zhang Bo, Guo Yufeng, Tang Xinwei
Chin. J. Semicond.  2005, 26(11): 2154-2158
Abstract PDF

A novel SOI high voltage device structure with a shielding trench and its breakdown mode with a self-adapted interface charge are proposed.Interface charges that change with the drain voltage are introduced in the shielding trench.Interface charges enhance the vertical electric field of the buried layer and reduce that of the top Si layer simultaneously.Furthermore,they also modulate the surface electric field.So, interface charges shield the top Si layer from a high electric field.The breakdown voltage and electric field profile are researched for different device parameters for a ST structure by using a 2D device simulator.It is shown that the electric field of buried oxide increases from about 3ESi to 600V/μm.It breaks through the limitation of the sustained voltage of the buried oxide layer of a normal SOI device and enhances the breakdown voltage of the SOI device remarkably.

A novel SOI high voltage device structure with a shielding trench and its breakdown mode with a self-adapted interface charge are proposed.Interface charges that change with the drain voltage are introduced in the shielding trench.Interface charges enhance the vertical electric field of the buried layer and reduce that of the top Si layer simultaneously.Furthermore,they also modulate the surface electric field.So, interface charges shield the top Si layer from a high electric field.The breakdown voltage and electric field profile are researched for different device parameters for a ST structure by using a 2D device simulator.It is shown that the electric field of buried oxide increases from about 3ESi to 600V/μm.It breaks through the limitation of the sustained voltage of the buried oxide layer of a normal SOI device and enhances the breakdown voltage of the SOI device remarkably.
A Breakdown Model of Thin Drift Region LDMOS with a Step Doping Profile
Li Qi, Zhang Bo, Li Zhaoji
Chin. J. Semicond.  2005, 26(11): 2159-2163
Abstract PDF

An analytical breakdown model for thin drift region RESURF LDMOS with a step doping profile is presented.Based on 2D Poisson equation,the derived model gives the solutions of the surface field distributions and the breakdown voltage.The influence of all design parameters on breakdown voltage is calculated.All analytical results are well verified by the numerical analysis obtained by the semiconductor device simulator MEDICI.The breakdown voltage of the step profile structure increases by a factor of 1.2 compared with the conventional RESURF device.

An analytical breakdown model for thin drift region RESURF LDMOS with a step doping profile is presented.Based on 2D Poisson equation,the derived model gives the solutions of the surface field distributions and the breakdown voltage.The influence of all design parameters on breakdown voltage is calculated.All analytical results are well verified by the numerical analysis obtained by the semiconductor device simulator MEDICI.The breakdown voltage of the step profile structure increases by a factor of 1.2 compared with the conventional RESURF device.
An Analytical Model for Polysilicon Quantization in MOS Devices
Dai Yuehua, Chen Junning, Ke Daoming, Sun Jiae, Xu Chao
Chin. J. Semicond.  2005, 26(11): 2164-2168
Abstract PDF

This paper proposes a model for polysilicon quantum effects in MOSFETs.Based on the least-squares curve fit,electron distribution functions are obtained.Then, solving Possion equations,a physically based analytical model is described.There are only two fitting parameters in the new model that can be used to describe different states such as accumulation,threshold,and strong inversion.However,different models used to depict those as different states,respectively.Additionally threshold voltages with the new model are calculated and compared with the numerical simulation results.The good agreement between them proves that the new model is correct and exact.

This paper proposes a model for polysilicon quantum effects in MOSFETs.Based on the least-squares curve fit,electron distribution functions are obtained.Then, solving Possion equations,a physically based analytical model is described.There are only two fitting parameters in the new model that can be used to describe different states such as accumulation,threshold,and strong inversion.However,different models used to depict those as different states,respectively.Additionally threshold voltages with the new model are calculated and compared with the numerical simulation results.The good agreement between them proves that the new model is correct and exact.
Modeling and Simulation of Hot-Carrier Degradation in Deep-Submicron pMOSFET’s
Li Kang, Hao Yue, Liu Hongxia, Fang Jianping, Xue Hongmin
Chin. J. Semicond.  2005, 26(11): 2169-2174
Abstract PDF

A HCI (hot carrier injection) degradation model of DSM(deep submicron) pMOSFETs is studied.A physical description of a time-dependent gate current is given with a stream function analysis.Based on this model,the HCI degradation model of DSM pMOSFETs is updated.A kind of reliability simulation method for HCI degradation, based on the degradation model, is then proposed,which is used to predict the degree of HCI degradation of the devices under static stress.Analysis and comparisons of simulation results are also given.This kind of simulation method is used in XDRT tools for HCI reliability analysis of pMOSFET devices.

A HCI (hot carrier injection) degradation model of DSM(deep submicron) pMOSFETs is studied.A physical description of a time-dependent gate current is given with a stream function analysis.Based on this model,the HCI degradation model of DSM pMOSFETs is updated.A kind of reliability simulation method for HCI degradation, based on the degradation model, is then proposed,which is used to predict the degree of HCI degradation of the devices under static stress.Analysis and comparisons of simulation results are also given.This kind of simulation method is used in XDRT tools for HCI reliability analysis of pMOSFET devices.
III-V Compound HBT Modeling
Liu Jun, Sun Lingling
Chin. J. Semicond.  2005, 26(11): 2175-2181
Abstract PDF

Accurate modeling of the microwave characteristics of III-V compound heterojunction bipolar transistors(HBT's) is extremely useful for microwave power applications of the device.A new large-signal for III-V HBT devices,which is valid for DC,small- and large-signal AC operation, is developed.The model may be used for self-heating effects which are very important for HBT’s.Through the use of several novel features,the proposed approach is differentiated from the UCSD HBT or VBIC BJT representations.Simulation results are verified with comparisons to DC,S-parameters, and large-signal measurements.

Accurate modeling of the microwave characteristics of III-V compound heterojunction bipolar transistors(HBT's) is extremely useful for microwave power applications of the device.A new large-signal for III-V HBT devices,which is valid for DC,small- and large-signal AC operation, is developed.The model may be used for self-heating effects which are very important for HBT’s.Through the use of several novel features,the proposed approach is differentiated from the UCSD HBT or VBIC BJT representations.Simulation results are verified with comparisons to DC,S-parameters, and large-signal measurements.
A LC Voltage-Controlled Oscillator Tuned by Switched Step Capacitors:Part II,Circuit Design and Implementation
Tang Zhangwen, He Jie, Min Hao
Chin. J. Semicond.  2005, 26(11): 2182-2190
Abstract PDF

A novel LC oscillator differentially tuned by switched step capacitors,which is implemented in a CMOS 0.25μm 1P4M CMOS process,is proposed to verify our theoretical analysis of tuning characteristics.The tuning capacitance of the proposed switched step capacitors is 146% of the conventional inversion-MOS varactors’.In the 1/f~3 region,the novel differentially tuned topology has 7dB phase noise reduction compared to the single-ended tuned topology.The implemented VCO at 1.013GHz has a phase noise of -83,-107, and -130dBc/Hz, at a 10kHz,100kHz, and 1MHz offset,respectively.Power consumption is 8.6mW.

A novel LC oscillator differentially tuned by switched step capacitors,which is implemented in a CMOS 0.25μm 1P4M CMOS process,is proposed to verify our theoretical analysis of tuning characteristics.The tuning capacitance of the proposed switched step capacitors is 146% of the conventional inversion-MOS varactors’.In the 1/f~3 region,the novel differentially tuned topology has 7dB phase noise reduction compared to the single-ended tuned topology.The implemented VCO at 1.013GHz has a phase noise of -83,-107, and -130dBc/Hz, at a 10kHz,100kHz, and 1MHz offset,respectively.Power consumption is 8.6mW.
A Ku Band HFET MMIC VCO with Source Terminal Tuning
Wang Shaodong, Gao Xuebang, Wu Hongjiang, Wu Ahui
Chin. J. Semicond.  2005, 26(11): 2191-2195
Abstract PDF

Based on S-parameter and negative impedance analyses,a Ku band HFET MMIC VCO,which is turned at source, is designed and fabricated successfully for the first time.A large signal model is developed to perform nonlinear analysis.A two dimensional impedance sweep is used to determine the output impedance network match in gate and source ports.The measurement results show that a 16dBm output power over a 17.79~17.89GHz frequency range is achieved.

Based on S-parameter and negative impedance analyses,a Ku band HFET MMIC VCO,which is turned at source, is designed and fabricated successfully for the first time.A large signal model is developed to perform nonlinear analysis.A two dimensional impedance sweep is used to determine the output impedance network match in gate and source ports.The measurement results show that a 16dBm output power over a 17.79~17.89GHz frequency range is achieved.
Simulation of EI-Interface Voltage in an EIS-Type Semiconductor Biochemical Sensor
Jia Yunfang, Niu Wencheng, Zhang Fuhai, Liu Guohua, Yu Mei
Chin. J. Semicond.  2005, 26(11): 2196-2201
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An EI(electrolyte insulator)-interface voltage model suitable for EIS(electrolyte insulator semiconductor) sensor is proposed.Based on this model a CAA program is developed.Using this program,the voltage distribution of the double layer,density of electriferous sites, and EI-interface voltage are quantificationally analyzed.Finally, to certify this model,the contrast of the simulated results with the experiment data of ISFET (ion sensitive field effect transistor) is given.

An EI(electrolyte insulator)-interface voltage model suitable for EIS(electrolyte insulator semiconductor) sensor is proposed.Based on this model a CAA program is developed.Using this program,the voltage distribution of the double layer,density of electriferous sites, and EI-interface voltage are quantificationally analyzed.Finally, to certify this model,the contrast of the simulated results with the experiment data of ISFET (ion sensitive field effect transistor) is given.
A New Type of CMOS Temperature Sensor
Zhang Xun, Wang Peng, Jin Dongming
Chin. J. Semicond.  2005, 26(11): 2202-2207
Abstract PDF

Theory and design of compatible wide range smart temperature sensors in standard CMOS technology is presented.The simulated temperature sensitivity using a CSMC 06μm mixed-signal CMOS process is –1.15μA/℃ (over the temperature range of -40~125℃) and the measured is –0.99μA/℃.The power dissipation of the sensor is 1.5mW at a 5V voltage supply,and the chip area is 0.025mm2.The characteristics of this sensor make it especially suitable for low-cost high-volume integrated microsystems over a wide range of fields,such as automotive,oil prospecting,biomedical,and consumer.

Theory and design of compatible wide range smart temperature sensors in standard CMOS technology is presented.The simulated temperature sensitivity using a CSMC 06μm mixed-signal CMOS process is –1.15μA/℃ (over the temperature range of -40~125℃) and the measured is –0.99μA/℃.The power dissipation of the sensor is 1.5mW at a 5V voltage supply,and the chip area is 0.025mm2.The characteristics of this sensor make it especially suitable for low-cost high-volume integrated microsystems over a wide range of fields,such as automotive,oil prospecting,biomedical,and consumer.
A RF Integrated Inductor with CoZrO Ferrite Thin Film
Yang Chen, Liu Feng, Ren Tianling, Liu Litian, Feng Haigang, Wang Zihui, Long Haibo, Yu Jun
Chin. J. Semicond.  2005, 26(11): 2208-2212
Abstract PDF

A novel RF integrated inductor with ferrite thin-film is fabricated.The inductor has a simple structure of "SiO2 insulating layer/magnetic thin-film (CoZrO) /SiO2 insulating layer/Cu coils" ,in which a planar single-turn metal coil and a CoZrO ferrite thin-film fabricated by the Sol-Gel method are used.The fabrication process is compatible with standard integrated process.Inductors without the magnetic thin-film are fabricated as the referential sample using the same processes,in which the structure parameters are consistent with the inductor with magnetic thin-film.The inductance (L) of the inductor with magnetic thin-film is 175nH and the quality factor (Q) is 18.5 at 2GHz.Compared with the inductor without magnetic thin-film,L and Q are raised by 25% and 23%,respectively.

A novel RF integrated inductor with ferrite thin-film is fabricated.The inductor has a simple structure of "SiO2 insulating layer/magnetic thin-film (CoZrO) /SiO2 insulating layer/Cu coils" ,in which a planar single-turn metal coil and a CoZrO ferrite thin-film fabricated by the Sol-Gel method are used.The fabrication process is compatible with standard integrated process.Inductors without the magnetic thin-film are fabricated as the referential sample using the same processes,in which the structure parameters are consistent with the inductor with magnetic thin-film.The inductance (L) of the inductor with magnetic thin-film is 175nH and the quality factor (Q) is 18.5 at 2GHz.Compared with the inductor without magnetic thin-film,L and Q are raised by 25% and 23%,respectively.
Characteristic Analysis on High Power GaInP/AlGaInP Semiconductor Laser Diodes
Xu Yun, Guo Liang, Cao Qing, Song Guofeng, Gan Qiaoqiang, Yang Guohua, Li Yuzhang, Chen Lianghui
Chin. J. Semicond.  2005, 26(11): 2213-2217
Abstract PDF

High power AlGaInP compressively strained separate confinement heterojunction quantum well laser diodes with real refractive index are successfully fabricated.The epitaxial growth of the laser is carried out by a one-step MOCVD using a 15 degree -misoriented GaAs substrate.The laser diodes have a ridge-waveguide with a 3μm-wide,900μm-long, and 5%/95% coating.The typical threshold current of these devices is 32mA,the COD threshold is 88mW,and the continuous wave operation current and slope efficiency at 80mW are 110mA and 1W/A,respectively.Stable fundamental-mode operation at 60mW is obtained and the full angles at half-maximum power, perpendicular and parallel to the junction plane, are 32 degree and 10 degree,respectively.The lasing wavelength is 658.4nm.The internal loss is 4.1cm-1, the internal quantum efficiency is 80%, and the transparent current density is 648A/cm2.

High power AlGaInP compressively strained separate confinement heterojunction quantum well laser diodes with real refractive index are successfully fabricated.The epitaxial growth of the laser is carried out by a one-step MOCVD using a 15 degree -misoriented GaAs substrate.The laser diodes have a ridge-waveguide with a 3μm-wide,900μm-long, and 5%/95% coating.The typical threshold current of these devices is 32mA,the COD threshold is 88mW,and the continuous wave operation current and slope efficiency at 80mW are 110mA and 1W/A,respectively.Stable fundamental-mode operation at 60mW is obtained and the full angles at half-maximum power, perpendicular and parallel to the junction plane, are 32 degree and 10 degree,respectively.The lasing wavelength is 658.4nm.The internal loss is 4.1cm-1, the internal quantum efficiency is 80%, and the transparent current density is 648A/cm2.
Fabrication of a Novel Si-Based Thermo-Optical Tunable Flat-Top Filter with Narrow Band
Zuo Yuhua, Cai Xiao, Mao Rongwei, Wang Qiming
Chin. J. Semicond.  2005, 26(11): 2218-2222
Abstract PDF

Based on a step-type F-P cavity structure,a novel all Si-based thermo-optical tunable flat-top filter with narrow band is fabricated,using our patent SOR(silicon-on-reflector) bonding technology.The device demonstrates a flat-top width of 2nm,3dB band of 4.4nm,FSR(free spectra range) of 8.5nm,and a red-shift of the transmittance peak of 33nm under the applied voltage.

Based on a step-type F-P cavity structure,a novel all Si-based thermo-optical tunable flat-top filter with narrow band is fabricated,using our patent SOR(silicon-on-reflector) bonding technology.The device demonstrates a flat-top width of 2nm,3dB band of 4.4nm,FSR(free spectra range) of 8.5nm,and a red-shift of the transmittance peak of 33nm under the applied voltage.
硅基M×N型微环阵列谐振滤波器的理论分析
Yan Xin, Ma Chunsheng, Xu Yuanzhe, Wang Xianyin, E Shulin, Zhang Daming
Chin. J. Semicond.  2005, 26(11): 2223-2229
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A 10bit, 50Msample/s,57.6mW CMOS Pipeline A/D Converter
Huang Feipeng, Wang Jingguang, He Jirou, Hong Zhiliang
Chin. J. Semicond.  2005, 26(11): 2230-2235
Abstract PDF

A 10bit 50MS/s CMOS pipeline A/D converter is implemented in a 1.8V,0.18μm CMOS process.Circuit techniques used to achieve low power consumption include a dynamic comparator,an optimal capacitor, and OTA.Resetting T/H and MADC is adopted to cancel the offset of the OTA.the non-dominant pole of the OTA is optimized to make the OTA work stably.Measured performances include –0.6~0.7LSB of DNL and 44.9dB of SINAD with 5.1MHz input at 50Msample/s.The ADC,with a 57.6mW power consumption and a 0.8mV input offset,occupies a core area of 0.52mm2.

A 10bit 50MS/s CMOS pipeline A/D converter is implemented in a 1.8V,0.18μm CMOS process.Circuit techniques used to achieve low power consumption include a dynamic comparator,an optimal capacitor, and OTA.Resetting T/H and MADC is adopted to cancel the offset of the OTA.the non-dominant pole of the OTA is optimized to make the OTA work stably.Measured performances include –0.6~0.7LSB of DNL and 44.9dB of SINAD with 5.1MHz input at 50Msample/s.The ADC,with a 57.6mW power consumption and a 0.8mV input offset,occupies a core area of 0.52mm2.
Analysis of Phase Relations in MMI Couplers with a Positional Number of 2
Sun Yiling, Jiang Xiaoqing, Yang Jianyi, Wang Minghua
Chin. J. Semicond.  2005, 26(11): 2236-2240
Abstract PDF

Based on the self-imaging effect of multimode interference couplers,the phase relations in multimode interference couplers with a positional number of 2 are discussed.The phases of the self-images are directly related to the input position.Expressions of the phases are derived.The guided-mode propagation analysis method is used to confirm the analytical results.

Based on the self-imaging effect of multimode interference couplers,the phase relations in multimode interference couplers with a positional number of 2 are discussed.The phases of the self-images are directly related to the input position.Expressions of the phases are derived.The guided-mode propagation analysis method is used to confirm the analytical results.
Generation of Polynomial Response Surface Models for Sizing of an Analog IC
Gao Xuelian, Shi Yin
Chin. J. Semicond.  2005, 26(11): 2241-2247
Abstract PDF

This paper presents a new method for analog circuit sizing to generate polynomial response surface models of the performance characteristics of an analog IC.This method generates a performance model with SPICE device-level accuracy for linear or nonlinear circuits and composes a geometric program that fully describes the analog circuit sizing problem.The unknown parameters of the polynomial response surface models are positive real coefficients and random real exponents.And this model is changeable to realize the limits of precision.Results validate the effectiveness of this approach to generate polynomial response surface models for an op-amp circuit.

This paper presents a new method for analog circuit sizing to generate polynomial response surface models of the performance characteristics of an analog IC.This method generates a performance model with SPICE device-level accuracy for linear or nonlinear circuits and composes a geometric program that fully describes the analog circuit sizing problem.The unknown parameters of the polynomial response surface models are positive real coefficients and random real exponents.And this model is changeable to realize the limits of precision.Results validate the effectiveness of this approach to generate polynomial response surface models for an op-amp circuit.
A High Performance Differential Reference Voltage Generator Used in ADC
Li Dan, Ye Jinghua, Hong Zhiliang
Chin. J. Semicond.  2005, 26(11): 2248-2253
Abstract PDF

A differential reference voltage generator with low power consumption and good performance, which is used in ADC, is introduced.The high performance temperature-compensated reference current is generated with a new structure bandgap, and the current is converted to the needed reference directly through the transconductor buffer.The differential voltage has high precision,low temperature-drift, and good anti-jamming ability.The circuit is realized with the TSMC 0.18μm CMOS process and the die area is 250μm×350μm.The chip has been tested.The power consumption is 0.9mW and the average temperature coefficient of the output differential reference voltage is 9.5e-6K-1.

A differential reference voltage generator with low power consumption and good performance, which is used in ADC, is introduced.The high performance temperature-compensated reference current is generated with a new structure bandgap, and the current is converted to the needed reference directly through the transconductor buffer.The differential voltage has high precision,low temperature-drift, and good anti-jamming ability.The circuit is realized with the TSMC 0.18μm CMOS process and the die area is 250μm×350μm.The chip has been tested.The power consumption is 0.9mW and the average temperature coefficient of the output differential reference voltage is 9.5e-6K-1.
Analysis and Improvement on the High Frequency Effect of TO Packaging for Photodiodes
Zhang Shangjian, Liu Jian, Wen Jimin, Zhu Ninghua
Chin. J. Semicond.  2005, 26(11): 2254-2258
Abstract PDF

Two methods for analyzing the high frequency effect of the packaging techniques for photodiodes are presented.The first method compares the frequency responses of the photodiode before and after packaging,and the second one is based on the relations between the scattering parameters of the packaging network,photodiode chip,and module.In the experiment of the TO photodiode module,results from the two methods show coherence,which indicates that the methods established are effective for practical applications.Analysis results also denote that there is a resonance between the inductance in the bonding wire and the parasitic capacitance in both the feedthru of the TO header and the photodiode chip.This resonance can be used to compensate for the overall frequency response of the device.By adjusting the values of the inductance and capacitance,an optimized frequency response of the TO photodiode module is achieved.

Two methods for analyzing the high frequency effect of the packaging techniques for photodiodes are presented.The first method compares the frequency responses of the photodiode before and after packaging,and the second one is based on the relations between the scattering parameters of the packaging network,photodiode chip,and module.In the experiment of the TO photodiode module,results from the two methods show coherence,which indicates that the methods established are effective for practical applications.Analysis results also denote that there is a resonance between the inductance in the bonding wire and the parasitic capacitance in both the feedthru of the TO header and the photodiode chip.This resonance can be used to compensate for the overall frequency response of the device.By adjusting the values of the inductance and capacitance,an optimized frequency response of the TO photodiode module is achieved.
Corrosive Effect of Slurry Inhibitor on Copper Wafer
Li Xiujuan, Jin Zhuji, Kang Renke, Guo Dongming, Su Jianxiu
Chin. J. Semicond.  2005, 26(11): 2259-2263
Abstract PDF

Using Fe(NO3)3 as an oxidant and several selected corrosive inhibitors,the corrosive efficiency of slurries is investigated on a deposited copper wafer with a surface roughness of 1.42nm .The electrochemical behavior of the slurry is investigated by potentiodynamic polarization studies.The inhibition efficiency of the related corrosive inhibitors is calculated from the polarization data.The static etching rate and the polishing material removal rate are obtained.Atom force microscopy is used to measure the surface topography of corrosive copper film and the value of surface roughness is obtained by the ZYGO surface meters.The result shows that the benzotriazole (BTA) is a perfect corrosive inhibitor for the copper slurry.The inhibitor efficiency of the 1.5wt% Fe(NO3)3+ 0.1wt%BTA is 99.1% according to the potentiodynamic parameters.Either in the etching state or the polishing state,BTA has perfect ability to protect the surface of the copper wafer from corrosion.

Using Fe(NO3)3 as an oxidant and several selected corrosive inhibitors,the corrosive efficiency of slurries is investigated on a deposited copper wafer with a surface roughness of 1.42nm .The electrochemical behavior of the slurry is investigated by potentiodynamic polarization studies.The inhibition efficiency of the related corrosive inhibitors is calculated from the polarization data.The static etching rate and the polishing material removal rate are obtained.Atom force microscopy is used to measure the surface topography of corrosive copper film and the value of surface roughness is obtained by the ZYGO surface meters.The result shows that the benzotriazole (BTA) is a perfect corrosive inhibitor for the copper slurry.The inhibitor efficiency of the 1.5wt% Fe(NO3)3+ 0.1wt%BTA is 99.1% according to the potentiodynamic parameters.Either in the etching state or the polishing state,BTA has perfect ability to protect the surface of the copper wafer from corrosion.
TECHNICAL PROGRESS
Fabrication of ZnO Light-Emitting Diode by Using MOCVD Method
Ye Zhizhen, Xu Weizhong, Zeng Yujia, Jiang Liu, Zhao Binghui, Zhu Liping, Lü Jianguo, Huang Jingyun, Wang Lei, Li Xianhang
Chin. J. Semicond.  2005, 26(11): 2264-2266
Abstract PDF

p-type zinc oxide (ZnO) thin films are grown by plasma-assisted metalorganic chemical vapor deposition (MOCVD).A ZnO homostructural light-emitting diode is fabricated by growing p-type ZnO epi-layer on n-type bulk ZnO wafer. The room temperature electroluminescence spectrum from violet to green regions is observed while the ZnO-LED is supplied with a DC voltage.

p-type zinc oxide (ZnO) thin films are grown by plasma-assisted metalorganic chemical vapor deposition (MOCVD).A ZnO homostructural light-emitting diode is fabricated by growing p-type ZnO epi-layer on n-type bulk ZnO wafer. The room temperature electroluminescence spectrum from violet to green regions is observed while the ZnO-LED is supplied with a DC voltage.