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Volume 27, Issue 9, Sep 2006
Column
LETTERS
MOCVD-Grown AlGaN/AlN/GaN HEMT Structure with High Mobility GaN Thin Layer as Channel on SiC
Wang Xiaoliang, Hu Guoxin, Ma Zhiyong, Xiao Hongling, Wang Cuimei, Luo Weijun, Liu Xinyu, Chen Xiaojuan, Li Jianping, Li Jinmin, Qian He, Wang Zhanguo
Chin. J. Semicond.  2006, 27(9): 1521-1525
Abstract PDF

AlGaN/AlN/GaN high electron mobility transistor (HEMT) structures with a high-mobility GaN thin layer as a channel are grown on high resistive 6H-SiC substrates by metalorganic chemical vapor deposition.The HEMT structure exhibits a typical two-dimensional electron gas (2DEG) mobility of 1944cm2/(V·s) at room temperature and 11588cm2/(V·s) at 80K with almost equal 2DEG concentrations of about 1.03E13cm-2.High crystal quality of the HEMT structures is confirmed by triple-crystal X-ray diffraction analysis.Atomic force microscopy measurements reveal a smooth AlGaN surface with a root-mean-square roughness of 0.27nm for a scan area of 10μm×10μm.HEMT devices with 0.8μm gate length and 1.2mm gate width are fabricated using the structures.A maximum drain current density of 957mA/mm and an extrinsic transconductance of 267mS/mm are obtained.

AlGaN/AlN/GaN high electron mobility transistor (HEMT) structures with a high-mobility GaN thin layer as a channel are grown on high resistive 6H-SiC substrates by metalorganic chemical vapor deposition.The HEMT structure exhibits a typical two-dimensional electron gas (2DEG) mobility of 1944cm2/(V·s) at room temperature and 11588cm2/(V·s) at 80K with almost equal 2DEG concentrations of about 1.03E13cm-2.High crystal quality of the HEMT structures is confirmed by triple-crystal X-ray diffraction analysis.Atomic force microscopy measurements reveal a smooth AlGaN surface with a root-mean-square roughness of 0.27nm for a scan area of 10μm×10μm.HEMT devices with 0.8μm gate length and 1.2mm gate width are fabricated using the structures.A maximum drain current density of 957mA/mm and an extrinsic transconductance of 267mS/mm are obtained.
Study on the Characteristics of SOI DTMOS with Reverse Schottky Barriers
Bi Jinshun, Hai Chaohe
Chin. J. Semicond.  2006, 27(9): 1526-1530
Abstract PDF

Silicon-on-insulator dynamic threshold voltage MOSFETs with TiSi2/p-Si as reverse Schottky barriers (RSB) are presented.With this RSB scheme,DTMOS can operate beyond 0.7V,thus overcoming the drawback of DTMOS with the gate and body connected.The experimental results demonstrate that the threshold voltage in DT mode with an RSB is reduced by about 200mV at room temperature.SOI MOSFETs in DT mode with an RSB have advantages such as excellent subthreshold slope and high drivability over those under normal mode operation.The breakdown characteristics of SOI MOSFETs in the off-state are compared for the DT mode with RSB,floating body mode,normal mode.

Silicon-on-insulator dynamic threshold voltage MOSFETs with TiSi2/p-Si as reverse Schottky barriers (RSB) are presented.With this RSB scheme,DTMOS can operate beyond 0.7V,thus overcoming the drawback of DTMOS with the gate and body connected.The experimental results demonstrate that the threshold voltage in DT mode with an RSB is reduced by about 200mV at room temperature.SOI MOSFETs in DT mode with an RSB have advantages such as excellent subthreshold slope and high drivability over those under normal mode operation.The breakdown characteristics of SOI MOSFETs in the off-state are compared for the DT mode with RSB,floating body mode,normal mode.
Automatic IQ Phase Calibration Design in a 2.4GHz Direct Conversion Receiver
Liu Ruifeng, Li Yongming, Chen Hongyi,
Chin. J. Semicond.  2006, 27(9): 1531-1536
Abstract PDF

An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed.It uses a delay locked loop (DLL) with a proposed quadrature phase detector to greatly reduce the phase error.The receiver is fabricated in a 0.18μm CMOS process.Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.

An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed.It uses a delay locked loop (DLL) with a proposed quadrature phase detector to greatly reduce the phase error.The receiver is fabricated in a 0.18μm CMOS process.Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.
First-Principle Calculation of the Electronic Structure of Sb-Doped SrTiO3
Yun Jiangni, Zhang Zhiyong, Deng Zhouhu, Zhang Fuchun
Chin. J. Semicond.  2006, 27(9): 1537-1542
Abstract PDF

The electronic structure,including band structure,density of states (DOS),and partial density of states of SrTi1-xSbxO.3 with x=0,0.125,0.25,and 0.33 is calculated from the first principles of plane wave ultra-soft pseudo-potential technology based on density function theory.The calculated results reveal that due to the electron doping,the Fermi level moves into the conduction bands for SrTi1-xSbxO.3 with x=0.125 and the system shows metallic behavior.In addition,the DOS moves towards low energy and the optical band gap is broadened.The wide band gap and the low density of the states in the conduction band result in the transparency of the films.

The electronic structure,including band structure,density of states (DOS),and partial density of states of SrTi1-xSbxO.3 with x=0,0.125,0.25,and 0.33 is calculated from the first principles of plane wave ultra-soft pseudo-potential technology based on density function theory.The calculated results reveal that due to the electron doping,the Fermi level moves into the conduction bands for SrTi1-xSbxO.3 with x=0.125 and the system shows metallic behavior.In addition,the DOS moves towards low energy and the optical band gap is broadened.The wide band gap and the low density of the states in the conduction band result in the transparency of the films.
A 2GHz Low Power Differentially Tuned CMOS Monolithic LC-VCO
Zhang Li, Chi Baoyong, Yao Jinke, Wang Zhihua, Chen Hongyi
Chin. J. Semicond.  2006, 27(9): 1543-1547
Abstract PDF

A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process.The VCO has a 16.15% tuning range (from 1.8998 to 2.2335GHz) through a combination of analog and digital tuning techniques (4-bit binary switch-capacitor array).The measured phase noise is -118.17dBc/Hz at a 1MHz offset from a 2.158GHz carrier.With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits.The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors.The VCO draws a current of about 2.1mA from a 1.8V power supply and works normally with a 1.5V power supply.

A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process.The VCO has a 16.15% tuning range (from 1.8998 to 2.2335GHz) through a combination of analog and digital tuning techniques (4-bit binary switch-capacitor array).The measured phase noise is -118.17dBc/Hz at a 1MHz offset from a 2.158GHz carrier.With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits.The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors.The VCO draws a current of about 2.1mA from a 1.8V power supply and works normally with a 1.5V power supply.
A New Structure for a CMOS Audio Power AMP with Extremely Low THD and Low Power Consumption
Cao Zhengxin, Xiong Shaozhen
Chin. J. Semicond.  2006, 27(9): 1552-1556
Abstract PDF

A new system-corrected CMOS audio power AMP is presented.Consisting of four single-end OPAs,this structure is a pseudo-differential system.Compared to conventional CMOS power AMPs,it has the merits of low power consumption,extremely low THD,easy compensation,and good driving capability.With 1st silicon 0.25μm 1P4M CMOS technology and a 3V power supply,the output range can be 4Vpp when driving an 8Ω‖300pF load,while its power dissipation is less than 3mW.The THD is better than 0.003% at 1kHz.A new over-current protection circuit,which can effectively protect the power output circuits on the chip,is also demonstrated.

A new system-corrected CMOS audio power AMP is presented.Consisting of four single-end OPAs,this structure is a pseudo-differential system.Compared to conventional CMOS power AMPs,it has the merits of low power consumption,extremely low THD,easy compensation,and good driving capability.With 1st silicon 0.25μm 1P4M CMOS technology and a 3V power supply,the output range can be 4Vpp when driving an 8Ω‖300pF load,while its power dissipation is less than 3mW.The THD is better than 0.003% at 1kHz.A new over-current protection circuit,which can effectively protect the power output circuits on the chip,is also demonstrated.
A Radial Stub Test Circuit for Microwave Power Devices
Luo Weijun, Chen Xiaojuan, Liang Xiaoxin, Ma Xiaolin, Liu Xinyu, Wang Xiaoliang
Chin. J. Semicond.  2006, 27(9): 1557-1561
Abstract PDF

With the principles of microwave circuits and semiconductor device physics,two microwave power device test circuits combined with a test fixture are designed and simulated,whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz.The simulation and experimental results verify that the test circuit with a radial stub is better than that without.As an example,a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture.With a 5.4GHz microwave input signal,the maximum gain is 8.75dB,and the maximum output power is 33.2dBm.

With the principles of microwave circuits and semiconductor device physics,two microwave power device test circuits combined with a test fixture are designed and simulated,whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz.The simulation and experimental results verify that the test circuit with a radial stub is better than that without.As an example,a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture.With a 5.4GHz microwave input signal,the maximum gain is 8.75dB,and the maximum output power is 33.2dBm.
A New AC Driving Method for a Current-Programmed AM-OLED Pixel Circuit
Si Yujuan, Xu Yanlei, Lang Liuqi, Chen Xinfa, Liu Shiyong
Chin. J. Semicond.  2006, 27(9): 1562-1565
Abstract PDF

A new,improved pixel-driving circuit is presented based on a current-programmed pixel circuit in order to achieve an AC-driving mode.This driving method realizes an AC-driving mode,removes the threshold voltage variation of the driving TFT due to the process variation or long-term operation,which can bring about brightness non-uniformity,and eliminates high peak pulse currents at the beginning and end of recovery time.Simulation is done with AIM-SPICE,and simulation results demonstrate that the OLED is in the reverse-biased state during recovery time.

A new,improved pixel-driving circuit is presented based on a current-programmed pixel circuit in order to achieve an AC-driving mode.This driving method realizes an AC-driving mode,removes the threshold voltage variation of the driving TFT due to the process variation or long-term operation,which can bring about brightness non-uniformity,and eliminates high peak pulse currents at the beginning and end of recovery time.Simulation is done with AIM-SPICE,and simulation results demonstrate that the OLED is in the reverse-biased state during recovery time.
A General Method in the Synthesis of Ternary Double Pass-Transistor Circuits
Hang Guoqiang
Chin. J. Semicond.  2006, 27(9): 1566-1571
Abstract PDF

A general method for designing ternary circuits using double pass-transistor logic is investigated.The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits.A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented.This new static ternary double pass-transistor logic scheme has some favorable properties:the use of standard CMOS process without any modification of the thresholds,a perfectly symmetrical structure,a full logic swing,the maximum possible noise margins,a less complex structure,and no static power consumption.HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.

A general method for designing ternary circuits using double pass-transistor logic is investigated.The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits.A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented.This new static ternary double pass-transistor logic scheme has some favorable properties:the use of standard CMOS process without any modification of the thresholds,a perfectly symmetrical structure,a full logic swing,the maximum possible noise margins,a less complex structure,and no static power consumption.HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.
A Passive Low-Pass Filter on Low-Loss Substrate
Fang Jie, Liu Zewen, Zhao Jiahao, Chen Zhongmin, Wei Jia, Liu Litian, Li Zhijian
Chin. J. Semicond.  2006, 27(9): 1572-1577
Abstract PDF

The loss mechanisms of different passive devices (on-chip inductors and capacitors) on different substrates are analyzed and compared.OPS (oxidized porous silicon) and HR (high-resistivity) substrates are used as low-loss substrates for on-chip planar LPF (low pass filter) fabrication.For the study of substrate loss,a planar coil inductor is also designed.Simulation results show that Q (the quality factor) of the inductor on both substrates is over 20.Measurements of the LPF on OPS substrate give a -3dB bandwidth of 2.9GHz and a midband insertion loss of 0.87dB at 500MHz.The LPF on HR substrate gives a -3dB bandwidth of 2.3GHz and a midband insertion loss of 0.42dB at 500MHz.

The loss mechanisms of different passive devices (on-chip inductors and capacitors) on different substrates are analyzed and compared.OPS (oxidized porous silicon) and HR (high-resistivity) substrates are used as low-loss substrates for on-chip planar LPF (low pass filter) fabrication.For the study of substrate loss,a planar coil inductor is also designed.Simulation results show that Q (the quality factor) of the inductor on both substrates is over 20.Measurements of the LPF on OPS substrate give a -3dB bandwidth of 2.9GHz and a midband insertion loss of 0.87dB at 500MHz.The LPF on HR substrate gives a -3dB bandwidth of 2.3GHz and a midband insertion loss of 0.42dB at 500MHz.
PAPERS
Design,Analysis,and Optimization of a CMOS Active Pixel Sensor
Xu Jiangtao, Yao Suying, Li Binqiao, Shi Zaifeng, Gao Jing
Chin. J. Semicond.  2006, 27(9): 1548-1551
Abstract PDF

A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed.The circuit is embedded in a 64×64 pixel array CMOS image sensor and successfully taped out with a Chartered 0.35μm process.The pixel pitch is 8μm×8μm with a fill factor of 57%,the photo-sensitivity is 0.8V/(lux·s),and the dynamic range is 50dB.Theoretical analysis and test results indicate that as the process is scaled down,a smaller pixel pitch reduces the sensitivity.A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.

A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed.The circuit is embedded in a 64×64 pixel array CMOS image sensor and successfully taped out with a Chartered 0.35μm process.The pixel pitch is 8μm×8μm with a fill factor of 57%,the photo-sensitivity is 0.8V/(lux·s),and the dynamic range is 50dB.Theoretical analysis and test results indicate that as the process is scaled down,a smaller pixel pitch reduces the sensitivity.A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.
Preparation of AlSb Polycrystalline Thin Films by Co-Evaporation
Yao Feifei, Lei Zhi, , Feng Lianghuan, Zhang Jingquan, Li Wei, Wu Lili
Chin. J. Semicond.  2006, 27(9): 1578-1581
Abstract PDF

AlSb polycrystalline thin films are prepared by vacuum co-evaporation and post-annealing.The structural,optical,and electrical properties of the films are studied.X-ray diffraction results show that the films annealed at 540℃ are polycrystalline AlSb with a single-phase fcc structure.Optical transmission measurements indicate an indirect optical band gap of 1.62eV.The activation energy of conductivity is 0.33eV,as derived from the relation of dark conductivity versus temperature.These results show that AlSb thin films could become important materials for novel solar cells.

AlSb polycrystalline thin films are prepared by vacuum co-evaporation and post-annealing.The structural,optical,and electrical properties of the films are studied.X-ray diffraction results show that the films annealed at 540℃ are polycrystalline AlSb with a single-phase fcc structure.Optical transmission measurements indicate an indirect optical band gap of 1.62eV.The activation energy of conductivity is 0.33eV,as derived from the relation of dark conductivity versus temperature.These results show that AlSb thin films could become important materials for novel solar cells.
Current Oscillation Properties of Manganese-Doped-Silicon Materials
Chen Zhaoyang, Ba Weizhen, Zhang Jian, Cong Xiuyun, Bakhadyrkhanov M K, Zikrillaev N F
Chin. J. Semicond.  2006, 27(9): 1582-1585
Abstract PDF

Compensated material Si∶(B,Mn) is prepared by high temperature diffusion.The relation between the current oscillation parameters of this material and light intensity and electric field is studied.The experiment shows that:(1) In certain light intensity and electric field ranges (145~305V/cm) the material Si∶(B,Mn) with a resistivity of 1E4Ω·cm exhibits a current oscillation phenomenon at liquid nitrogen temperature;(2) At a certain electric field,the waveform of the current oscillation is stable and does not change with time;(3) The dependence relation between the oscillation frequency and light-intensity can be expressed by f=f0(L/L0)α where L0 is the minimum light-intensity needed to stimulate oscillation,f0 is the frequency under L0,L is the intensity of the light,and α is a coefficient that increase with electric field;(4) The modulating coefficient K (K=(Imax-Imin)/Imax) decreases as the light increases;(5) The maximum value of the oscillation Imax decreases with the increase of the light-intensity while the minimum value of oscillation Imin increases slowly.

Compensated material Si∶(B,Mn) is prepared by high temperature diffusion.The relation between the current oscillation parameters of this material and light intensity and electric field is studied.The experiment shows that:(1) In certain light intensity and electric field ranges (145~305V/cm) the material Si∶(B,Mn) with a resistivity of 1E4Ω·cm exhibits a current oscillation phenomenon at liquid nitrogen temperature;(2) At a certain electric field,the waveform of the current oscillation is stable and does not change with time;(3) The dependence relation between the oscillation frequency and light-intensity can be expressed by f=f0(L/L0)α where L0 is the minimum light-intensity needed to stimulate oscillation,f0 is the frequency under L0,L is the intensity of the light,and α is a coefficient that increase with electric field;(4) The modulating coefficient K (K=(Imax-Imin)/Imax) decreases as the light increases;(5) The maximum value of the oscillation Imax decreases with the increase of the light-intensity while the minimum value of oscillation Imin increases slowly.
Preparation of Si/SiO2 Optical Thin Film by Double Source Electron Beam Evaporation Technology
Zhao Miao, Zhou Daibing, Tan Manqing, Wang Xiaodong, Wu Xuming
Chin. J. Semicond.  2006, 27(9): 1586-1589
Abstract PDF

A technology for preparing optical thin films is introduced.A Si/SiO2 mixed thin film is evaporated onto K9 glass by double source electron beam evaporation.The results show that the reflectivity index of the mixed thin film changes with the proportion of the Si and SiO2 evaporation rate,and its value changes between that of Si and SiO2.The rules between the proportion of the evaporation rates and the reflectivity index is obtained through the experiment.The advantages of the technology are discussed.

A technology for preparing optical thin films is introduced.A Si/SiO2 mixed thin film is evaporated onto K9 glass by double source electron beam evaporation.The results show that the reflectivity index of the mixed thin film changes with the proportion of the Si and SiO2 evaporation rate,and its value changes between that of Si and SiO2.The rules between the proportion of the evaporation rates and the reflectivity index is obtained through the experiment.The advantages of the technology are discussed.
Photosensitive Barium Strontium Titanate Gel Films and Their Fine-Patterning
Zhang Weihua, Zhao Gaoyang, Li Ying, Zhao Wei
Chin. J. Semicond.  2006, 27(9): 1590-1594
Abstract PDF

A method is developed to fabricate fine patterns of BST films.With methanol as solvent,barium acetate,strontium chloride,and tetrabutyl titanate as starting materials,lactic acid as catalyzer,and Benzoylacetone (BzAcH) as chemical modifier,the photosensitive BST sols and their gel films with a chelate structure of ≡Ti-BzAc are prepared,both of which have good chemical stability at room atmosphere.The UV absorption peak of the chelate structure is located at about 358nm.The chelate structure can be dissociated using UV light from a high-pressure mercury lamp to irradiate the gel films,which shows the photosensitivity of the gel films.Due to the dissociation of the chelate structure,the solubility of the gel films in alcohol is remarkably decreased.Utilizing the photosensitivity,the BST gel films are irradiated by UV light through a pattern mask and leached by alcohol.The fine patterning of BST gel film is thus prepared.After annealing at 600℃,the fine patterning of BST films with perovskite structure and ferroelectric properties can be obtained.

A method is developed to fabricate fine patterns of BST films.With methanol as solvent,barium acetate,strontium chloride,and tetrabutyl titanate as starting materials,lactic acid as catalyzer,and Benzoylacetone (BzAcH) as chemical modifier,the photosensitive BST sols and their gel films with a chelate structure of ≡Ti-BzAc are prepared,both of which have good chemical stability at room atmosphere.The UV absorption peak of the chelate structure is located at about 358nm.The chelate structure can be dissociated using UV light from a high-pressure mercury lamp to irradiate the gel films,which shows the photosensitivity of the gel films.Due to the dissociation of the chelate structure,the solubility of the gel films in alcohol is remarkably decreased.Utilizing the photosensitivity,the BST gel films are irradiated by UV light through a pattern mask and leached by alcohol.The fine patterning of BST gel film is thus prepared.After annealing at 600℃,the fine patterning of BST films with perovskite structure and ferroelectric properties can be obtained.
Excessive Thermotaxis Effect of Low Current in pn Junction and Theoretical Analog Calculation
Miao Qinghai, Zhu Yangjun, Zhang Xinghua, Lu Shuojin
Chin. J. Semicond.  2006, 27(9): 1595-1599
Abstract PDF

When a transistor dissipates power on work,its junction temperature distribution is commonly non-uniform.Based on a sub-transistor shunt connection model,by theoretical analog calculation and experiment,it is found that in a non-uniform junction temperature distribution,the current density of the high-temperature region is higher than that of the low-temperature region.The ratio of the current density of the high-temperature region to that of the low-temperature region increases with the decrease of the measuring current.This phenomenon is called the excessive thermotaxis effect of low current.Based on these characteristics,the uniformity of the junction temperature distribution is studied.

When a transistor dissipates power on work,its junction temperature distribution is commonly non-uniform.Based on a sub-transistor shunt connection model,by theoretical analog calculation and experiment,it is found that in a non-uniform junction temperature distribution,the current density of the high-temperature region is higher than that of the low-temperature region.The ratio of the current density of the high-temperature region to that of the low-temperature region increases with the decrease of the measuring current.This phenomenon is called the excessive thermotaxis effect of low current.Based on these characteristics,the uniformity of the junction temperature distribution is studied.
Characteristics of npn AlGaN/GaN HBT
Gong Xin, Ma Lin, Zhang Xiaoju, Zhang Jinfeng, Yang Yan, Hao Yue
Chin. J. Semicond.  2006, 27(9): 1600-1603
Abstract PDF

A modeling of the minority carrier lifetime and impact ionization coefficients of GaN is presented.Then the simulation of an npn AlGaN/GaN heterojunction bipolar transistor (HBT) using a drift-diffusion transport model is executed.The turn-on,offset,and saturation voltages of the device are expressed analytically.Simulation results show that the high turn-on,offset,and saturation voltages of the practical device result from the high base sheet resistance and the nonohmic characteristics of the base contact,which are a reference for the device fabrication.

A modeling of the minority carrier lifetime and impact ionization coefficients of GaN is presented.Then the simulation of an npn AlGaN/GaN heterojunction bipolar transistor (HBT) using a drift-diffusion transport model is executed.The turn-on,offset,and saturation voltages of the device are expressed analytically.Simulation results show that the high turn-on,offset,and saturation voltages of the practical device result from the high base sheet resistance and the nonohmic characteristics of the base contact,which are a reference for the device fabrication.
Fabrication of a New-Layout InGaP/GaAs HBT
Yang Wei, Liu Xunchun, , Zhu Min, Wang Runmei
Chin. J. Semicond.  2006, 27(9): 1604-1607
Abstract PDF

The HBT is one of the most important devices in microwave and millimeter wave fields due to its outstanding performance and high reliability.A novel-layout HBT that employs a three-finger emitter is demonstrated.Compared to an HBT with a two-finger emitter,this device has good process tolerance,high yield,and good uniformity.Furthermore,it has superior DC and high-frequency characteristics.

The HBT is one of the most important devices in microwave and millimeter wave fields due to its outstanding performance and high reliability.A novel-layout HBT that employs a three-finger emitter is demonstrated.Compared to an HBT with a two-finger emitter,this device has good process tolerance,high yield,and good uniformity.Furthermore,it has superior DC and high-frequency characteristics.
Total Dose Gamma Irradiation Effects and AnnealingCharacteristics of a SiGe HBT
Niu Zhenhong, Guo Qi, Ren Diyuan, Liu Gang, Gao Song
Chin. J. Semicond.  2006, 27(9): 1608-1611
Abstract PDF

The total-dose radiation effects and annealing characteristics of a SiGe HBT are studied.It is found that the degradation of the current gain is dominated by the increase of Ib.The mechanisms behind the post-damage effects of total-dose radiation are discussed.The chief factor that causes post-damage effects is the increase in the interface states.

The total-dose radiation effects and annealing characteristics of a SiGe HBT are studied.It is found that the degradation of the current gain is dominated by the increase of Ib.The mechanisms behind the post-damage effects of total-dose radiation are discussed.The chief factor that causes post-damage effects is the increase in the interface states.
C-Band 3.5W/mm InGaP/GaAs HBT Power Transistors with >40% Power-Added Efficiency
Shen Huajun, Chen Yanhu, Yan Beiping, , Ge Ji, Wang Xiantai, Liu Xinyu
Chin. J. Semicond.  2006, 27(9): 1612-1615
Abstract PDF

A C-band InGaP/GaAs HBT power transistor with an optimized material structure and device peripheral structure is designed and fabricated by base-emitter metal self-aligning,emitter ballasting,and an electric plated air bridge.The measured BVCBO is greater than 31V and the BVCEO is greater than 21V.At a frequency of 5.4GHz,the saturated CW output power of the fabricated HBT power transistor is more than 1.4W with a maximum power density of 3.5W/mm,and the power added efficiency is greater than 40%.

A C-band InGaP/GaAs HBT power transistor with an optimized material structure and device peripheral structure is designed and fabricated by base-emitter metal self-aligning,emitter ballasting,and an electric plated air bridge.The measured BVCBO is greater than 31V and the BVCEO is greater than 21V.At a frequency of 5.4GHz,the saturated CW output power of the fabricated HBT power transistor is more than 1.4W with a maximum power density of 3.5W/mm,and the power added efficiency is greater than 40%.
An Accurate Arithmetic for On-Chip Spiral Inductors with Gradually Changed Metal Width and Space
Luo Tianxing, Shi Yanling, Ding Yanfang, Tang Shenqun, Liu Yun, Wang Yong, Zhu Jun, Chen Shoumian, Zhao Yuhang
Chin. J. Semicond.  2006, 27(9): 1616-1620
Abstract PDF

Compared with conventional passive inductors with fixed metal width and space,an inductor with gradually changed mental width and space is put forward to improve its quality factor.But it is difficult to get accurate inductance with most published formulas such as Jenei formula for such novel structure inductor.An accurate arithmetic is presented,which gets total self-inductance by adding up each turn’s self-inductance and gets mutual-inductance from an average approximate formula.The accuracy and effectiveness are verified by HFSS simulation and experiment measurement.The relative error for this arithmetic compared with HFSS is less than 3%,while compared with experiment measurements less than 4%.These show that it is efficient and valuable for the design of such passive spiral inductor.

Compared with conventional passive inductors with fixed metal width and space,an inductor with gradually changed mental width and space is put forward to improve its quality factor.But it is difficult to get accurate inductance with most published formulas such as Jenei formula for such novel structure inductor.An accurate arithmetic is presented,which gets total self-inductance by adding up each turn’s self-inductance and gets mutual-inductance from an average approximate formula.The accuracy and effectiveness are verified by HFSS simulation and experiment measurement.The relative error for this arithmetic compared with HFSS is less than 3%,while compared with experiment measurements less than 4%.These show that it is efficient and valuable for the design of such passive spiral inductor.
780nm InGaAsP/InGaP/AlGaAs High Power Semiconductor Laser
Cao Yulian, Lian Peng, Wang Qing, Wu Xuming, He Guorong, Cao Qing, Song Guofeng, Chen Lianghui
Chin. J. Semicond.  2006, 27(9): 1621-1624
Abstract PDF

Using metal organic chemical vapor deposition,we fabricate an InGaAsP/InGaP/AlGaAs single quantum well laser with a separate confinement heterostructure.We calculate the gain spectrum with and without the effect of interband relaxation.The peak wavelength of the PL spectrum is 764nm.Due to the In carry-over effect,the interface between InGaP and AlGaAs is not abrupt.The performance of the laser diodes into which a thin GaAsP interlayer is inserted is better than those with no such interlayer.The threshold current is decreased from 560 to 450mA,the slope efficiency is increased from 0.61 to 0.7W/A,and the output power is increased from 370 to 940mW.

Using metal organic chemical vapor deposition,we fabricate an InGaAsP/InGaP/AlGaAs single quantum well laser with a separate confinement heterostructure.We calculate the gain spectrum with and without the effect of interband relaxation.The peak wavelength of the PL spectrum is 764nm.Due to the In carry-over effect,the interface between InGaP and AlGaAs is not abrupt.The performance of the laser diodes into which a thin GaAsP interlayer is inserted is better than those with no such interlayer.The threshold current is decreased from 560 to 450mA,the slope efficiency is increased from 0.61 to 0.7W/A,and the output power is increased from 370 to 940mW.
Effects of a Microcavity on Harmonic and Intermodulation Distortionsof a Vertical Cavity Surface Emitting Laser
Zhang Bo, Lü Yinghua, Zhang Jinling
Chin. J. Semicond.  2006, 27(9): 1625-1629
Abstract PDF

The nonlinear effect of vertical cavity surface emitting lasers (VCSELs) is analyzed using the Volterra transfer function in analog modulation.The effects of the modulation frequency,spontaneous emission factor,and spontaneous emission lifetime on the third harmonic and third-order intermodulation distortions are investigated.The results show that nonlinear effect depends on spontaneous emission parameters.The control of the nonlinear effect,expanding of the modulation frequency,and improvement of performance and application of ROF system based on VCSELs can be achieved by manipulating the spontaneous emission parameters of VCSELs.

The nonlinear effect of vertical cavity surface emitting lasers (VCSELs) is analyzed using the Volterra transfer function in analog modulation.The effects of the modulation frequency,spontaneous emission factor,and spontaneous emission lifetime on the third harmonic and third-order intermodulation distortions are investigated.The results show that nonlinear effect depends on spontaneous emission parameters.The control of the nonlinear effect,expanding of the modulation frequency,and improvement of performance and application of ROF system based on VCSELs can be achieved by manipulating the spontaneous emission parameters of VCSELs.
Accurate Characterization for the Frequency Response of High-Speed Photodetectors
Wen Jimin, San Haisheng, Huang Hengpei, Xie Liang, Zhu Ninghua, Zhao Lingjuan, Wang Wei
Chin. J. Semicond.  2006, 27(9): 1630-1634
Abstract PDF

A novel optical heterodyne system with a distributed Bragg reflector (DBR) tunable laser is proposed,and an efficient calibration method is also put forward for removing errors caused by the fluctuations of optical power and the linewidth of the beat signal.Accurate frequency response of high-speed photodetectors can be obtained with this method.Results calibrated by our method agree well with data provided by the manufacturer,thereby demonstrating the accuracy and effectiveness of this method.Side-mode suppression ratios and dynamic behavior of wavelength transients, which probably affect the measurement of frequency response,are also investigated.

A novel optical heterodyne system with a distributed Bragg reflector (DBR) tunable laser is proposed,and an efficient calibration method is also put forward for removing errors caused by the fluctuations of optical power and the linewidth of the beat signal.Accurate frequency response of high-speed photodetectors can be obtained with this method.Results calibrated by our method agree well with data provided by the manufacturer,thereby demonstrating the accuracy and effectiveness of this method.Side-mode suppression ratios and dynamic behavior of wavelength transients, which probably affect the measurement of frequency response,are also investigated.
Damage Removal in GaN-LEDs by Two-Step Etching Technology
Song Yingping, Guo Xia, Ai Weiwei, Zhou Yueping, Shen Guangdi
Chin. J. Semicond.  2006, 27(9): 1635-1639
Abstract PDF

A two-step etching technology is used and the optimized etching parameter is found by experiment to remove etching damage in GaN-LEDs.The PL intensity of the sample etched by ICP with a power of 750W is decreased a little.The thickness of the etch damage layer is less than 25nm.The forward turn-on voltage and reverse leakage current of the LED that was etched by the two-step etching technology are reduced noticeably.The EL intensity is increased,indicating that the leakage current and the rate of nonradiative recombination both decreased.The optical efficiency and device reliability are also improved.

A two-step etching technology is used and the optimized etching parameter is found by experiment to remove etching damage in GaN-LEDs.The PL intensity of the sample etched by ICP with a power of 750W is decreased a little.The thickness of the etch damage layer is less than 25nm.The forward turn-on voltage and reverse leakage current of the LED that was etched by the two-step etching technology are reduced noticeably.The EL intensity is increased,indicating that the leakage current and the rate of nonradiative recombination both decreased.The optical efficiency and device reliability are also improved.
Fabrication of a High Quality Etching Mask for Two-Dimensional Photonic Crystal Structures
Du Wei, Xu Xingsheng, Han Weihua, Wang Chunxia, Zhang Yang, Yang Fuhua, Chen Hongda
Chin. J. Semicond.  2006, 27(9): 1640-1644
Abstract PDF

The influence of different fabrication parameters on polymethyl methacrylate (PMMA) etching mask for two-dimensional photonic crystal structures are studied.The results show that high quality PMMA etching mask can be realized by optimizing parameters such as PMMA thickness,electron beam exposure dose,developing time,and fixation time.

The influence of different fabrication parameters on polymethyl methacrylate (PMMA) etching mask for two-dimensional photonic crystal structures are studied.The results show that high quality PMMA etching mask can be realized by optimizing parameters such as PMMA thickness,electron beam exposure dose,developing time,and fixation time.
Silicon Nanowires Fabricated by MEMS Technology and Their Electronic Performance
Liu Wenping, Li Tie, Yang Heng, Jiao Jiwei, Li Xinxin, Wang Yuelin
Chin. J. Semicond.  2006, 27(9): 1645-1649
Abstract PDF

A novel diameter-controllable on-chip silicon nanowire is fabricated by traditional MEMS technology on a silicon-on-insulator substrate.The thickness of the nanowires is determined by thermal oxidation,and the width is achieved in the nanometer scale by isotropic and anisotropic self-stop etching with masks of SiO2 and Si3N4.SEM photos of the nanowires indicate that the thickness and width of the nanowires are both less than 100nm and the thinnest one is less than 20nm.The electronic properties of the as-released silicon nanowires are different from those with thick oxide shells.Their resistance increases gradually with time as they are exposed to air.Further experiments show that the adsorption of water plays a key role in the process.

A novel diameter-controllable on-chip silicon nanowire is fabricated by traditional MEMS technology on a silicon-on-insulator substrate.The thickness of the nanowires is determined by thermal oxidation,and the width is achieved in the nanometer scale by isotropic and anisotropic self-stop etching with masks of SiO2 and Si3N4.SEM photos of the nanowires indicate that the thickness and width of the nanowires are both less than 100nm and the thinnest one is less than 20nm.The electronic properties of the as-released silicon nanowires are different from those with thick oxide shells.Their resistance increases gradually with time as they are exposed to air.Further experiments show that the adsorption of water plays a key role in the process.
A Test System for the in situ Extraction of the Material Parameters of MEMS Thin Films
Huang Qing'an, Liu Zutao, Li Weihua, Li Qiaoping
Chin. J. Semicond.  2006, 27(9): 1650-1656
Abstract PDF

A new system for thein situ extraction of the material parameters of MEMS films is presented. The system is composed of three parts,including the layout of testing structures,test equipments,and a software application for analysis and control.Both the test and measurement signals of the test system are electrical,making it compatible with IC testing and capable for rapid testing.The measurement is executed automatically under the control of a computer.

A new system for thein situ extraction of the material parameters of MEMS films is presented. The system is composed of three parts,including the layout of testing structures,test equipments,and a software application for analysis and control.Both the test and measurement signals of the test system are electrical,making it compatible with IC testing and capable for rapid testing.The measurement is executed automatically under the control of a computer.
A 30nA Temperature-Independent CMOS Current Reference and Its Application in an LDO
Wang Yi, He Le’nian, Yan Xiaolang
Chin. J. Semicond.  2006, 27(9): 1657-1662
Abstract PDF

A high-precision CMOS current reference circuit is proposed for using in low-dropout (LDO) voltage regulators with low power.A current reference of 30nA,independent of supply voltage,is obtained with the sub-threshold region design method.In the high temperature region,taking advantage of the reverse current of the parasitic diode in the MOS transistor,every branch current in the current mirror is compensated,so that the precision of the 30nA current reference is improved from ±1nA to ±0.6nA in the range of -40~130℃.Using this current reference,the total quiescent current of the LDO is around 4μA in the range of -40~130℃.The proposed circuit is simulated using Spectre from Candence,and the chip is implemented in CSMC 0.5μm mixed-signal technology.The designed circuit is validated by the results of the chip test.

A high-precision CMOS current reference circuit is proposed for using in low-dropout (LDO) voltage regulators with low power.A current reference of 30nA,independent of supply voltage,is obtained with the sub-threshold region design method.In the high temperature region,taking advantage of the reverse current of the parasitic diode in the MOS transistor,every branch current in the current mirror is compensated,so that the precision of the 30nA current reference is improved from ±1nA to ±0.6nA in the range of -40~130℃.Using this current reference,the total quiescent current of the LDO is around 4μA in the range of -40~130℃.The proposed circuit is simulated using Spectre from Candence,and the chip is implemented in CSMC 0.5μm mixed-signal technology.The designed circuit is validated by the results of the chip test.
Study on the Automatic Compensation of a Sagnac Loop Filter
Liu Lihui, Chen Shaohua, Zhao Qida, Liu Yuliang, Li Fang
Chin. J. Semicond.  2006, 27(9): 1663-1665
Abstract PDF

We present a novel automatic compensation method in which a Sagnac loop filter is fixed to a material with a large thermal expansion constant.Its temperature sensitivity can reach 0.059nm/℃,which is as 0.04 times as that of an uncompensated Sagnac loop filter.This method benefits the practicality of Sagnac loop filters to a certain extent.

We present a novel automatic compensation method in which a Sagnac loop filter is fixed to a material with a large thermal expansion constant.Its temperature sensitivity can reach 0.059nm/℃,which is as 0.04 times as that of an uncompensated Sagnac loop filter.This method benefits the practicality of Sagnac loop filters to a certain extent.
A Highly Linear CMOS IF Variable Gain Amplifier withExponential Gain Control
Yun Tinghua, Tang Shoulong, Shi Longxing
Chin. J. Semicond.  2006, 27(9): 1666-1671
Abstract PDF

A highly linear intermediate frequency variable gain amplifier (VGA) with exponential gain control is developed using a transconductance linearization scheme.It consists of a variable-gain cell based on a current-steering structure,a novel wide-range exponential voltage generator,and a stage of a fixed-gain amplifier.The VGA is fabricated in 0.25μm CMOS technology. Measurements show that a continuous-gain control range of 8~48dB and a 3rd intermodulation distortion of better than -60dBc at a differential output of 1V peak-to-peak are obtained.The noise figure at maximum gain is 8.7dB,and the OIP3 loaded with 50Ω is 14.2dBm.

A highly linear intermediate frequency variable gain amplifier (VGA) with exponential gain control is developed using a transconductance linearization scheme.It consists of a variable-gain cell based on a current-steering structure,a novel wide-range exponential voltage generator,and a stage of a fixed-gain amplifier.The VGA is fabricated in 0.25μm CMOS technology. Measurements show that a continuous-gain control range of 8~48dB and a 3rd intermodulation distortion of better than -60dBc at a differential output of 1V peak-to-peak are obtained.The noise figure at maximum gain is 8.7dB,and the OIP3 loaded with 50Ω is 14.2dBm.
Application of Two Thermal Actuators in Miniature Electric Field Sensors
Ye Chao, Chen Xianxiang, Peng Chunrong, Tao Hu, Xia Shanhong
Chin. J. Semicond.  2006, 27(9): 1672-1675
Abstract PDF

This paper presents two novel miniature electrostatic field sensors with thermal actuators,one of which uses a chevron actuator array and the other of which uses amplification-compliant micro-transmission.A test system with a lock-in amplifier is constructed to detect the output signal of the sensor.The test results show that both of the two sensors respond to an external electric field linearly,but the sensor with amplification-compliant micro-transmissions has higher sensitivity.

This paper presents two novel miniature electrostatic field sensors with thermal actuators,one of which uses a chevron actuator array and the other of which uses amplification-compliant micro-transmission.A test system with a lock-in amplifier is constructed to detect the output signal of the sensor.The test results show that both of the two sensors respond to an external electric field linearly,but the sensor with amplification-compliant micro-transmissions has higher sensitivity.
Temperature Sensors Based on CMOS Sub-Threshold Characteristic
Zhang Xun, Wang Peng, Jin Dongming
Chin. J. Semicond.  2006, 27(9): 1676-1680
Abstract PDF

The design of a compatible wide-range low-power smart temperature sensor based on the CMOS sub-threshold characteristic is presented for the purpose of on-chip temperature measure and protection from overheating.Simulated with CSMC 0.6μm mixed-signal CMOS technology,the circuit works well over the temperature range from -50 to 150℃.For the amplifier feedback,it has a high power supply rejection ratio under VDD from 2 to 6V.Measurements support the simulation result. The temperature sensitivity is 0.77V/℃.The power dissipation of the sensor is 16μA because the bias current is generated by the CMOS sub-threshold characteristic.The chip area is 300μm×250μm.The characteristics of this sensor make it especially suitable for low-cost high-volume integrated microsystems over a wide range of fields,such as computer,automotive,and biomedical.

The design of a compatible wide-range low-power smart temperature sensor based on the CMOS sub-threshold characteristic is presented for the purpose of on-chip temperature measure and protection from overheating.Simulated with CSMC 0.6μm mixed-signal CMOS technology,the circuit works well over the temperature range from -50 to 150℃.For the amplifier feedback,it has a high power supply rejection ratio under VDD from 2 to 6V.Measurements support the simulation result. The temperature sensitivity is 0.77V/℃.The power dissipation of the sensor is 16μA because the bias current is generated by the CMOS sub-threshold characteristic.The chip area is 300μm×250μm.The characteristics of this sensor make it especially suitable for low-cost high-volume integrated microsystems over a wide range of fields,such as computer,automotive,and biomedical.
2.5Gb/s Mixed-Integrated Optical Transmitters
Feng Jun, Shi Wei, Miao Yu, Li Lianming, Zhang Jun, Wang Zhigong, Jiang Shan
Chin. J. Semicond.  2006, 27(9): 1681-1685
Abstract PDF

A transmitter for fiber optical communication is realized using hybrid integration technology.The laser diode and the chip of the laser diode driver and the 4∶1 multiplexer,which are realized in different materials and processes,are fabricated on one same ceramic substrate using a film circuit to make up one opto-electronic integrated circuit,i.e.,an OEIC.The chip and the diode are realized with a 0.35μm CMOS process and with wet etching,polymer planar, and lift-off technologies, respectively.The module is encapsulated with a wing shell.Some parameters of the transmitter are summed as follows:bit rate:2.5GB/s,wave length:1550nm,output optical power:5.5dBm,extraction ratio:9.4dB.

A transmitter for fiber optical communication is realized using hybrid integration technology.The laser diode and the chip of the laser diode driver and the 4∶1 multiplexer,which are realized in different materials and processes,are fabricated on one same ceramic substrate using a film circuit to make up one opto-electronic integrated circuit,i.e.,an OEIC.The chip and the diode are realized with a 0.35μm CMOS process and with wet etching,polymer planar, and lift-off technologies, respectively.The module is encapsulated with a wing shell.Some parameters of the transmitter are summed as follows:bit rate:2.5GB/s,wave length:1550nm,output optical power:5.5dBm,extraction ratio:9.4dB.
Research on a Measurement Circuit for UDSM CMOSProcess Parameter Variation
Yang Yuan, Gao Yong, Yu Ningmei
Chin. J. Semicond.  2006, 27(9): 1686-1689
Abstract PDF

The main device parameter variations for UDSM processes are discussed briefly.Based on the "amplifying" idea,simple circuits for measuring the gate delay,dynamic power,leakage power,and their variations for a 90nm process are designed.A novel circuit that can get the gate delay variation curve for a UDSM process using shorter inverter link is presented.The circuits are fabricated using 90nm CMOS technology,and the variation curve for the 90nm CMOS process is obtained.The results show that the variation range is 178.6%,194.0% for dynamic power,and 19.5 times for leakage power.Thus the leakage power variation is the most serious.

The main device parameter variations for UDSM processes are discussed briefly.Based on the "amplifying" idea,simple circuits for measuring the gate delay,dynamic power,leakage power,and their variations for a 90nm process are designed.A novel circuit that can get the gate delay variation curve for a UDSM process using shorter inverter link is presented.The circuits are fabricated using 90nm CMOS technology,and the variation curve for the 90nm CMOS process is obtained.The results show that the variation range is 178.6%,194.0% for dynamic power,and 19.5 times for leakage power.Thus the leakage power variation is the most serious.
Suppressing of On-Chip Inductor Current Crowding by a Multi-Current-Path Method
Liu Ke, , Jian Hongyan, Huang Chenling, Tang Zhangwen
Chin. J. Semicond.  2006, 27(9): 1690-1694
Abstract PDF

From the view of the electromagnetic theory,we examine the current redistributions of an inductor.We conclude that metal with a small cross-section has a weak skin effect and that inductors with a smaller ratio of the turn width to the space between turns have a weak proximity effect.The inductors are fabricated in 0.35μm four-metal CMOS technology.A turn of the differential inductor is divided into multi-shunt tracks,which keep the symmetry of the two ports of the inductor.Compared with a single-current-path configuration,the multi-current-path inductor offers a 40% greater maximum quality factor and a narrower range of operating frequencies,which we interpret here in detail.

From the view of the electromagnetic theory,we examine the current redistributions of an inductor.We conclude that metal with a small cross-section has a weak skin effect and that inductors with a smaller ratio of the turn width to the space between turns have a weak proximity effect.The inductors are fabricated in 0.35μm four-metal CMOS technology.A turn of the differential inductor is divided into multi-shunt tracks,which keep the symmetry of the two ports of the inductor.Compared with a single-current-path configuration,the multi-current-path inductor offers a 40% greater maximum quality factor and a narrower range of operating frequencies,which we interpret here in detail.
Thermal Fatigue Life Time Prediction of Sn-3.5Ag Lead-Free SolderJoint for Chip Scale Package
Han Xiao, Ding Han, Sheng Xinjun, Zhang Bo
Chin. J. Semicond.  2006, 27(9): 1695-1700
Abstract PDF

The thermal fatigue life time of Sn-3.5Ag lead-free solder joint of a chip scale package subjected to a thermal cycling load is predicted.Using the finite element analysis software ANSYS,a three dimensional symmetric model of the chip scale package is established,which uses the Anand constitutive model to describe the viscoplastic material property of Sn-3.5Ag lead-free solder joints.The deformation of the CSP package and the stress-strain variation of the solder joint under a thermal cycling load are investigated through thermal stress analysis.The Darveaux fatigue life prediction method is used to calculate the fatigue life time of the lead-free solder joint based on the finite element simulation results.

The thermal fatigue life time of Sn-3.5Ag lead-free solder joint of a chip scale package subjected to a thermal cycling load is predicted.Using the finite element analysis software ANSYS,a three dimensional symmetric model of the chip scale package is established,which uses the Anand constitutive model to describe the viscoplastic material property of Sn-3.5Ag lead-free solder joints.The deformation of the CSP package and the stress-strain variation of the solder joint under a thermal cycling load are investigated through thermal stress analysis.The Darveaux fatigue life prediction method is used to calculate the fatigue life time of the lead-free solder joint based on the finite element simulation results.