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Volume 29, Issue 1, Jan 2008
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LETTERS
The Bipolar Field-Effect Transistor:III.Short Channel Electrochemical Current Theory(Two-MOS-Gates on Pure-Base)
Jie Binbin, Sah Chih-Tang
J. Semicond.  2008, 29(1): 1-11
Abstract PDF

This paper describes the short channel theory of the bipolar field-effect transistor (BiFET) by partitioning the transistor into two sections,the source and drain sections,each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and electron-hole-channel components of the output and transfer currents and conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D.C.terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates (MOS-gates) on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the long physical channel currents and conductances from those of the short electrical channels are reported.

This paper describes the short channel theory of the bipolar field-effect transistor (BiFET) by partitioning the transistor into two sections,the source and drain sections,each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and electron-hole-channel components of the output and transfer currents and conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D.C.terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates (MOS-gates) on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the long physical channel currents and conductances from those of the short electrical channels are reported.
Low-Temperature Growth of ZnO Films on GaAs by Metal Organic Chemical Vapor Deposition
Shi Huiling, Ma Xiaoyu, Hu Like, Chong Feng
J. Semicond.  2008, 29(1): 12-16
Abstract PDF

ZnO thin films were grown on GaAs (001) substrates by metal-organic chemical vapor deposition (MOCVD) at low temperatures ranging from 100 to 400℃.DEZn and H2O were used as the zinc precursor and oxygen precursor,respectively.The effects of the growth temperatures on the growth characteristics and optical properties of ZnO films were investigated.The X-ray diffraction measurement (XRD) results indicated that all the thin films were grown with highly c-axis orientation.The surface morphologies and crystal properties of the films were critically dependent on the growth temperatures.Although there was no evidence of epitaxial growth,the scanning electron microscopy (SEM) image of ZnO film grown at 400℃ revealed the presence of ZnO microcrystallines with closed packed hexagon structure.The photoluminescence spectrum at room temperature showed only bright band-edge (3.33eV) emissions with little or no deep-level emission related to defects.

ZnO thin films were grown on GaAs (001) substrates by metal-organic chemical vapor deposition (MOCVD) at low temperatures ranging from 100 to 400℃.DEZn and H2O were used as the zinc precursor and oxygen precursor,respectively.The effects of the growth temperatures on the growth characteristics and optical properties of ZnO films were investigated.The X-ray diffraction measurement (XRD) results indicated that all the thin films were grown with highly c-axis orientation.The surface morphologies and crystal properties of the films were critically dependent on the growth temperatures.Although there was no evidence of epitaxial growth,the scanning electron microscopy (SEM) image of ZnO film grown at 400℃ revealed the presence of ZnO microcrystallines with closed packed hexagon structure.The photoluminescence spectrum at room temperature showed only bright band-edge (3.33eV) emissions with little or no deep-level emission related to defects.
Polysilicon Over-Etching Time Control of Advanced CMOS Processing with Emission Microscopy
Zhao Yi, Wan Xinggong
J. Semicond.  2008, 29(1): 17-19
Abstract PDF

The emission microscopy (EMMI) test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure,named a poly-edge structure.From the values of the breakdown voltage (Vbd) of MOS capacitors (poly-edge structure),it was observed that,with for the initial polysilicon etching-time,almost all capacitors in one wafer failed under the initial failure model.With the increase of polysilicon over-etching time,the number of the initial failure capacitors decreased.Finally,no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s.The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests.The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area,which will short the polysilicon gate with silicon substrate after the silicide process.

The emission microscopy (EMMI) test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure,named a poly-edge structure.From the values of the breakdown voltage (Vbd) of MOS capacitors (poly-edge structure),it was observed that,with for the initial polysilicon etching-time,almost all capacitors in one wafer failed under the initial failure model.With the increase of polysilicon over-etching time,the number of the initial failure capacitors decreased.Finally,no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s.The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests.The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area,which will short the polysilicon gate with silicon substrate after the silicide process.
A Solar-Blind AlGaN-Based p-i-n Back-Illuminated Photodetector with a High Temperature AlN Template Layer
Zou Zeya, Yang Mohua, Liu Ting, Zhao Wenbo, Zhao Hong, Luo Muchang, Wang Zhen
J. Semicond.  2008, 29(1): 20-23
Abstract PDF

The growth,fabrication,and characterization of a solar-blind AlGaN-based p-i-n back-illuminated photodetector with a high temperature AlN template are reported for the first time.The photodetector was fabricated from multilayer AlxGa1-xN films grown by MOCVD on double-polished c-plane (0001) sapphire substrates.Crack free,high Al content (0.7) AlGaN multilayer structure,designed for the solar-blind p-i-n back-illuminated photodetector,was grown on a high temperature AlN template without a nuclear layer.The high quality of the epitaxial layers is demonstrated by in-situ optical reflectance monitoring curve,triple-axis X-ray diffraction,and atomic-force microscope.At a 1.8V bias,the processed p-i-n photodetector exhibits a solar-blind photoresponse with a maximum responsivity of 0.0864A/W at 270nm.The photodetector exhibits a forward turn-on voltage at around 3.5V and a reverse breakdown voltage above 20V,and the leakage current is below 20pA for 2V reverse bias.

The growth,fabrication,and characterization of a solar-blind AlGaN-based p-i-n back-illuminated photodetector with a high temperature AlN template are reported for the first time.The photodetector was fabricated from multilayer AlxGa1-xN films grown by MOCVD on double-polished c-plane (0001) sapphire substrates.Crack free,high Al content (0.7) AlGaN multilayer structure,designed for the solar-blind p-i-n back-illuminated photodetector,was grown on a high temperature AlN template without a nuclear layer.The high quality of the epitaxial layers is demonstrated by in-situ optical reflectance monitoring curve,triple-axis X-ray diffraction,and atomic-force microscope.At a 1.8V bias,the processed p-i-n photodetector exhibits a solar-blind photoresponse with a maximum responsivity of 0.0864A/W at 270nm.The photodetector exhibits a forward turn-on voltage at around 3.5V and a reverse breakdown voltage above 20V,and the leakage current is below 20pA for 2V reverse bias.
A Near-1V 10ppm/℃ CMOS Bandgap Reference with Curvature Compensation
Xing Xinpeng, Li Dongmei, Wang Zhihua
J. Semicond.  2008, 29(1): 24-28
Abstract PDF

A low voltage bandgap reference with curvature compensation is presented.Using current mode structure,the proposed bandgap circuit has a minimum voltage of 900mV.Compensated through the VEB linearization technique,this bandgap reference can reach a temperature coefficient of 10ppm/℃ from 0 to 150℃.With a 1.1V supply voltage,the supply current is 43μA and the PSRR is 55dB at DC frequency.This bandgap reference has been verified in a UMC 0.18μm mixed mode CMOS technology and occupies 0.186mm2 of chip area.

A low voltage bandgap reference with curvature compensation is presented.Using current mode structure,the proposed bandgap circuit has a minimum voltage of 900mV.Compensated through the VEB linearization technique,this bandgap reference can reach a temperature coefficient of 10ppm/℃ from 0 to 150℃.With a 1.1V supply voltage,the supply current is 43μA and the PSRR is 55dB at DC frequency.This bandgap reference has been verified in a UMC 0.18μm mixed mode CMOS technology and occupies 0.186mm2 of chip area.
PAPERS
Optical and Electrical Properties of GaN:Mg Grown by MOCVD
Wang Lili, Zhang Shuming, Yang Hui, Liang Junwu
J. Semicond.  2008, 29(1): 29-32
Abstract PDF

Mg-doped GaN layers prepared by metalorganic chemical vapor deposition were annealed at temperatures between 550 and 950℃.Room temperature (RT) Hall and photoluminescence (PL) spectroscopy measurements were performed on the as-grown and annealed samples.After annealing at 850℃,a high hole concentration of 8e17cm-3 and a resistivity of 0.8Ω·cm are obtained.Two dominant defect-related PL emission bands in GaN:Mg are investigated;the blue band is centered at 2.8eV (BL) and the ultraviolet emission band is around 3.27eV (UVL).The relative intensity of BL to UVL increases after annealing at 550℃,but decreases when the annealing temperature is raised from 650 to 850℃,and finally increases sharply when the annealing temperature is raised to 950℃.The hole concentration increases with increased Mg doping,and decreases for higher Mg doping concentrations.These results indicate that the difficulties in achieving high hole concentration of 1e18cm-3 appear to be related not only to hydrogen passivation,but also to self-compensation.

Mg-doped GaN layers prepared by metalorganic chemical vapor deposition were annealed at temperatures between 550 and 950℃.Room temperature (RT) Hall and photoluminescence (PL) spectroscopy measurements were performed on the as-grown and annealed samples.After annealing at 850℃,a high hole concentration of 8e17cm-3 and a resistivity of 0.8Ω·cm are obtained.Two dominant defect-related PL emission bands in GaN:Mg are investigated;the blue band is centered at 2.8eV (BL) and the ultraviolet emission band is around 3.27eV (UVL).The relative intensity of BL to UVL increases after annealing at 550℃,but decreases when the annealing temperature is raised from 650 to 850℃,and finally increases sharply when the annealing temperature is raised to 950℃.The hole concentration increases with increased Mg doping,and decreases for higher Mg doping concentrations.These results indicate that the difficulties in achieving high hole concentration of 1e18cm-3 appear to be related not only to hydrogen passivation,but also to self-compensation.
Organic Light-Emitting Diodes by Doping Liq into an Electron Transport Layer
Xu Wei, Lu Fuhan, Jiang Xueyin, Zhang Zhilin, Zhu Wenqing, Xu Gui
J. Semicond.  2008, 29(1): 33-38
Abstract PDF

Organic light emitting diodes (OLEDs) incorporating an n-doping transport layer comprised of 8-hydroxy-quinolinato lithium (Liq) doped into 4’7- diphyenyl-1,10-phenanthroline (BPhen) as ETL and a p-doping transport layer that includes tetrafluro-tetracyano-quinodimethane (F4- TCNQ) doped into 4,4′,4" -tris (3-methylphenylphenylamono) triphenylamine (m-MTDATA) are demonstrated.In order to examine the improvement in the conductivity of transport layers,hole-only and electron-only devices are fabricated.The current and power efficiency of organic light-emitting diodes are improved significantly after introducing an n-doping (BPhen:33wt% Liq) layer as an electron transport layer (ETL) and a p-doping layer composed of m-MTDATA and F4- TCNQ as a hole transport layer (HTL).Compared with the control device (without doping),the current efficiency and power efficiency of the most efficient device (device C) are enhanced by approximately 51% and 89%,respectively,while driving voltage is reduced by 29%.This improvement is attributed to the improved conductivity of the transport layers that leads to efficient charge balance in the emission zone.

Organic light emitting diodes (OLEDs) incorporating an n-doping transport layer comprised of 8-hydroxy-quinolinato lithium (Liq) doped into 4’7- diphyenyl-1,10-phenanthroline (BPhen) as ETL and a p-doping transport layer that includes tetrafluro-tetracyano-quinodimethane (F4- TCNQ) doped into 4,4′,4" -tris (3-methylphenylphenylamono) triphenylamine (m-MTDATA) are demonstrated.In order to examine the improvement in the conductivity of transport layers,hole-only and electron-only devices are fabricated.The current and power efficiency of organic light-emitting diodes are improved significantly after introducing an n-doping (BPhen:33wt% Liq) layer as an electron transport layer (ETL) and a p-doping layer composed of m-MTDATA and F4- TCNQ as a hole transport layer (HTL).Compared with the control device (without doping),the current efficiency and power efficiency of the most efficient device (device C) are enhanced by approximately 51% and 89%,respectively,while driving voltage is reduced by 29%.This improvement is attributed to the improved conductivity of the transport layers that leads to efficient charge balance in the emission zone.
RTD’s Relaxation Oscillation Characteristics with Applied Pressure
Tong Zhaomin, Xue Chenyang, Zhang Binzhen, Liu Jun, Qiao Hui
J. Semicond.  2008, 29(1): 39-44
Abstract PDF

The relaxation oscillation characteristics of a resonant tunneling diode (RTD) with applied pressure are reported.The oscillation circuit is simulated and designed by Pspice 8.0,and the measured oscillation frequency is up to 200kHz.Using molecular beam epitaxy (MBE),AlAs/InxGa1-xAs/GaAs double barrier resonant tunneling structures (DBRTS) are grown on (100) semi-insulated (SI) GaAs substrate,and the RTD is processed by Au/Ge/Ni/Au metallization and an air-bridge structure.Because of the piezoresistive effect of RTD,with Raman spectrum to measure the applied pressure,the relaxation oscillation characteristics have been studied,which show that the relaxation oscillation frequency has approximately a -17.9kHz/MPa change.

The relaxation oscillation characteristics of a resonant tunneling diode (RTD) with applied pressure are reported.The oscillation circuit is simulated and designed by Pspice 8.0,and the measured oscillation frequency is up to 200kHz.Using molecular beam epitaxy (MBE),AlAs/InxGa1-xAs/GaAs double barrier resonant tunneling structures (DBRTS) are grown on (100) semi-insulated (SI) GaAs substrate,and the RTD is processed by Au/Ge/Ni/Au metallization and an air-bridge structure.Because of the piezoresistive effect of RTD,with Raman spectrum to measure the applied pressure,the relaxation oscillation characteristics have been studied,which show that the relaxation oscillation frequency has approximately a -17.9kHz/MPa change.
A Temperature-Dependent Model for Threshold Voltage and Potential Distribution of Fully Depleted SOI MOSFETs
Tang Junxiong, Tang Minghua, Yang Feng, Zhang Junjie, Zhou Yichun, Zheng Xuejun
J. Semicond.  2008, 29(1): 45-49
Abstract PDF

A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors is developed.The two-dimensional potential distribution function in the silicon thin film based on an approximate parabolic function has been applied to solve the two-dimensional Poisson’s equation with suitable boundary conditions.The minimum of the surface potential is used to deduce the threshold voltage model.The model reveals the variations of potential distribution and threshold voltage with temperature,taking into account short-channel effects.Furthermore,the model is verified by the SILVACO ATLAS simulation.The calculations and the simulation agree well.

A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors is developed.The two-dimensional potential distribution function in the silicon thin film based on an approximate parabolic function has been applied to solve the two-dimensional Poisson’s equation with suitable boundary conditions.The minimum of the surface potential is used to deduce the threshold voltage model.The model reveals the variations of potential distribution and threshold voltage with temperature,taking into account short-channel effects.Furthermore,the model is verified by the SILVACO ATLAS simulation.The calculations and the simulation agree well.
Organic,Bistable Devices with AgTCNQ Charge Transfer Complex by Vacuum Co-Deposition
Tu Deyu, Ji Zhuoyu, Shang Liwei, Liu Ming, Wang Congshun, Hu Wenping
J. Semicond.  2008, 29(1): 50-54
Abstract PDF

The AgTCNQ thin-film was prepared by vacuum vapor co-deposition and characterized by infrared spectral analysis,and then a uniform AgTCNQ (TCNQ=7,7,8,8-tetracyanoquinodimethane) thin-film layer was sandwiched in a Ti/AgTCNQ/Au crossbar structure array as organic bistable devices (OBD).A reversible and reproducible memory switching property,caused by intermolecular charge transfer (CT) in the AgTCNQ thin-film,was observed in the organic bistable devices.The positive threshold voltage from the high impedance state to the low impedance was about 3.8~5V,with the reverse phenomenon occurring at a negative voltage of -3.5~-4.4V,lower than that with a CuTCNQ active layer.The crossbar array of OBDs with AgTCNQ is promising for nonvolatile organic memory applications.

The AgTCNQ thin-film was prepared by vacuum vapor co-deposition and characterized by infrared spectral analysis,and then a uniform AgTCNQ (TCNQ=7,7,8,8-tetracyanoquinodimethane) thin-film layer was sandwiched in a Ti/AgTCNQ/Au crossbar structure array as organic bistable devices (OBD).A reversible and reproducible memory switching property,caused by intermolecular charge transfer (CT) in the AgTCNQ thin-film,was observed in the organic bistable devices.The positive threshold voltage from the high impedance state to the low impedance was about 3.8~5V,with the reverse phenomenon occurring at a negative voltage of -3.5~-4.4V,lower than that with a CuTCNQ active layer.The crossbar array of OBDs with AgTCNQ is promising for nonvolatile organic memory applications.
A High-Efficiency Fiber-to-Waveguide Coupler with Low Polarization Dependence Using a Diluted Waveguide in InP Substrate with a 1.55μm Wavelength
Zhang Yun, Zuo Yuhua, Guo Jianchuan, Ding Wuchang, Cheng Buwen, Yu Jinzhong, Wang Qiming
J. Semicond.  2008, 29(1): 55-62
Abstract PDF

We propose a fiber-to-waveguide coupler for side-illuminated p-i-n photodiodes to obtain high responsivity and low polarization dependence that is grown on InP substrate and is suitable for surface hybrid integration in low cost modules.The fiber-to-waveguide coupler is based on a diluted waveguide,which is composed of ten periods of undoped 120nm InP /80nm InGaAsP (1.05μm bandgap) multiple layers.Using the semi-vectorial three dimensional beam propagation method (BPM) with the central difference scheme,the coupling efficiency of fiber-to-waveguide under different conditions is simulated and studied,and the optimized conditions for fiber-to-waveguide coupling are obtained.For TE-like and TM-like modes,the calculated maximum coupling efficiency is higher than 94% and 92%,respectively.The calculated polarization dependence is less than 0.1dB,showing good polarization independence.

We propose a fiber-to-waveguide coupler for side-illuminated p-i-n photodiodes to obtain high responsivity and low polarization dependence that is grown on InP substrate and is suitable for surface hybrid integration in low cost modules.The fiber-to-waveguide coupler is based on a diluted waveguide,which is composed of ten periods of undoped 120nm InP /80nm InGaAsP (1.05μm bandgap) multiple layers.Using the semi-vectorial three dimensional beam propagation method (BPM) with the central difference scheme,the coupling efficiency of fiber-to-waveguide under different conditions is simulated and studied,and the optimized conditions for fiber-to-waveguide coupling are obtained.For TE-like and TM-like modes,the calculated maximum coupling efficiency is higher than 94% and 92%,respectively.The calculated polarization dependence is less than 0.1dB,showing good polarization independence.
A 12~18GHz Wide Band VCO Based on Quasi-MMIC
Wang Shaodong, Gao Xuebang, Wu Hongjiang, Wang Xiangwei, Mo Lidong
J. Semicond.  2008, 29(1): 63-68
Abstract PDF

Using an in-house MMIC and an off-chip,high-quality varactor,a novel wide band VCO covered Ku band is introduced.In contrast to HMIC technology,this method reduces the complexity of microchip assembly.More importantly,it overcomes the constraint that the standard commercial GaAs pHEMT MMIC process is usually not compatible with high-quality varactors for VCO,and it significantly improves the phase noise and frequency tuning linearity performances compared to either MMIC or HMIC implementation.It is a novel and high-quality method to develop microwave and millimeter wave VCO.

Using an in-house MMIC and an off-chip,high-quality varactor,a novel wide band VCO covered Ku band is introduced.In contrast to HMIC technology,this method reduces the complexity of microchip assembly.More importantly,it overcomes the constraint that the standard commercial GaAs pHEMT MMIC process is usually not compatible with high-quality varactors for VCO,and it significantly improves the phase noise and frequency tuning linearity performances compared to either MMIC or HMIC implementation.It is a novel and high-quality method to develop microwave and millimeter wave VCO.
A Robust Low Power Chaos-Based Truly Random Number Generator
Zhou Tong, Zhou Zhibo, Yu Mingyan, Ye Yizheng
J. Semicond.  2008, 29(1): 69-74
Abstract PDF

This paper presents a low power,truly random number generator (TRNG) based on a simple chaotic map of the Bernoulli shift,which is extended to remain robustness in implementation.The map is realized by switched-current techniques that can fully integrate it in a cryptosystem on a chip.A pipelined architecture post-processed by a simple XOR circuit is used to improve the entropy.The TRNG is fabricated in an HJTC 0.18μm CMOS mixed signal process,and the statistical properties are investigated by measurement results.The power consumption is only 1.42mW and the truly random output bit rate is 10Mbit/s.

This paper presents a low power,truly random number generator (TRNG) based on a simple chaotic map of the Bernoulli shift,which is extended to remain robustness in implementation.The map is realized by switched-current techniques that can fully integrate it in a cryptosystem on a chip.A pipelined architecture post-processed by a simple XOR circuit is used to improve the entropy.The TRNG is fabricated in an HJTC 0.18μm CMOS mixed signal process,and the statistical properties are investigated by measurement results.The power consumption is only 1.42mW and the truly random output bit rate is 10Mbit/s.
A CMOS Dynamic Comparator for Pipelined ADCs with Improved Speed/Power Ratio
Liu Ke, Yang Haigang
J. Semicond.  2008, 29(1): 75-81
Abstract PDF

This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution.Because the architecture is based on the coupled current sources and differential input pairs,this comparator’s threshold voltage can be adjusted to a desired level.Compared with traditional comparators,this one shows significant improvement in area,power,and speed.Fabricated in 0.35μm CMOS technology,it occupies only 30μm×70μm.Simulation and measurement results indicate the comparator has a sampling frequency up to 1GHz with 2Vpp differential input signal range and only 181μW power consumption under a 3.3V supply.The speed/power ratio reaches up to 5524GS/J.

This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution.Because the architecture is based on the coupled current sources and differential input pairs,this comparator’s threshold voltage can be adjusted to a desired level.Compared with traditional comparators,this one shows significant improvement in area,power,and speed.Fabricated in 0.35μm CMOS technology,it occupies only 30μm×70μm.Simulation and measurement results indicate the comparator has a sampling frequency up to 1GHz with 2Vpp differential input signal range and only 181μW power consumption under a 3.3V supply.The speed/power ratio reaches up to 5524GS/J.
A Statistical Method for Characterizing CMOS Process Fluctuations in Subthreshold Current Mirrors
Zhang Lei, Yu Zhiping, He Xiangqing
J. Semicond.  2008, 29(1): 82-87
Abstract PDF

A novel method to characterize CMOS process fluctuations in subthreshold current mirrors (SCM) is reported.The proposed model is succinct in methodology and calculation complexity compared with previous statistical models.However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit,which makes it promising for engineering applications.The model statistically Abstracts physical parameters,which depend on the IC process,into random variables with certain mean values and standard deviations,while aggregating all the random impacts into a discrete martingale.The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to 1μA.The proposed theory successfully predicts ~10% of die-to-die fluctuation measured in the experiment,and also suggests the ~1mV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry.The deviations between calculated probabilities and measured data are less than 8%.Meanwhile,pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.

A novel method to characterize CMOS process fluctuations in subthreshold current mirrors (SCM) is reported.The proposed model is succinct in methodology and calculation complexity compared with previous statistical models.However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit,which makes it promising for engineering applications.The model statistically Abstracts physical parameters,which depend on the IC process,into random variables with certain mean values and standard deviations,while aggregating all the random impacts into a discrete martingale.The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to 1μA.The proposed theory successfully predicts ~10% of die-to-die fluctuation measured in the experiment,and also suggests the ~1mV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry.The deviations between calculated probabilities and measured data are less than 8%.Meanwhile,pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.
Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector
Chen Yingmei, Wang Zhigong, Zhang Li
J. Semicond.  2008, 29(1): 88-92
Abstract PDF

A fast-locking,low-jitter,phase-locked loop (PLL) with a simple phase-frequency detector is proposed.The phase-frequency detector is composed of only two XOR gates.It simultaneously achieves low jitter and short locking time.The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45° .The PLL is fabricated in 0.18μm CMOS technology.The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is -102.6dBc/Hz.The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps.The power dissipation excluding the output buffers is only 21.6mW at a 1.8V supply.

A fast-locking,low-jitter,phase-locked loop (PLL) with a simple phase-frequency detector is proposed.The phase-frequency detector is composed of only two XOR gates.It simultaneously achieves low jitter and short locking time.The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45° .The PLL is fabricated in 0.18μm CMOS technology.The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is -102.6dBc/Hz.The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps.The power dissipation excluding the output buffers is only 21.6mW at a 1.8V supply.
Low Power Design Orienting 384×288 Snapshot Infrared Readout Integrated Circuits
Liu Dan, Lu Wengao, Chen Zhongjian, Ji Lijiu, Zhao Baoying
J. Semicond.  2008, 29(1): 93-98
Abstract PDF

This paper presents a low power design for a 384×288 infrared (IR) readout integrated circuit (ROIC).For the character of IR detector (ro≈100kΩ,Iint≈100nA),a novel pixel structure called quad-share buffered direct injection (QSBDI) is proposed and realized.In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency,a stable bias,good FPN performance,and low power usage.This ROIC also supports two integration modes (integration then readout and integration while readout),two selectable gains,and four window readout modes.A test 128×128 ROIC is designed,fabricated,and tested.The test results show that the ROIC has good linearity.The peak to peak variance of the sub array is about 10mV.The power of pixel stage is only 1mW,and the total power dissipation is 37mW at a working frequency of 4MHz.

This paper presents a low power design for a 384×288 infrared (IR) readout integrated circuit (ROIC).For the character of IR detector (ro≈100kΩ,Iint≈100nA),a novel pixel structure called quad-share buffered direct injection (QSBDI) is proposed and realized.In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency,a stable bias,good FPN performance,and low power usage.This ROIC also supports two integration modes (integration then readout and integration while readout),two selectable gains,and four window readout modes.A test 128×128 ROIC is designed,fabricated,and tested.The test results show that the ROIC has good linearity.The peak to peak variance of the sub array is about 10mV.The power of pixel stage is only 1mW,and the total power dissipation is 37mW at a working frequency of 4MHz.
A Low-Power,Single-Poly,Non-Volatile Memory for Passive RFID Tags
Zhao Dixian, Yan Na, Xu Wen, Yang Liwu, Wang Junyu, Min Hao
J. Semicond.  2008, 29(1): 99-104
Abstract PDF

Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips.The memory bit cell is designed with conventional single-poly pMOS transistors,based on the bi-directional Fowler-Nordheim tunneling effect,and the typical program/erase time is 10ms for every 16bits.A new,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme.The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.

Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips.The memory bit cell is designed with conventional single-poly pMOS transistors,based on the bi-directional Fowler-Nordheim tunneling effect,and the typical program/erase time is 10ms for every 16bits.A new,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme.The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.
Bandgap Energies in Strain-Free Ga1-xInxNyAs-y/GaAs QWs After Annealing
Wen Yuhua, Tang Jiyu, Zhao Chuanzhen, Wu Liangzhen, Kong Yunting, Tang Lili, Liu Chao, Wu Lifeng, Li Shunfang, Chen Junfang
J. Semicond.  2008, 29(1): 105-109
Abstract PDF

According to the annealing-induced changes of an N-centered nearest-neighbor (NN) environment in Ga1-xInxNyAs-y quaternary alloys,we present a statistical distributing model of the binary bonds in a thermodynamics equilibrium state.Then,the parameter r,the calculated number of NN In atoms per N atom,is introduced into the BAC empirical model.Finally,bandgap energies in strain-free Ga1-xInxNyAs-y/GaAs QWs are calculated by discussing the boundary conditions for the electron wavefunction in the BAC model.

According to the annealing-induced changes of an N-centered nearest-neighbor (NN) environment in Ga1-xInxNyAs-y quaternary alloys,we present a statistical distributing model of the binary bonds in a thermodynamics equilibrium state.Then,the parameter r,the calculated number of NN In atoms per N atom,is introduced into the BAC empirical model.Finally,bandgap energies in strain-free Ga1-xInxNyAs-y/GaAs QWs are calculated by discussing the boundary conditions for the electron wavefunction in the BAC model.
A Simulation of the Capacitance-Voltage Characteristics of a Ge/Si Quantum-Well Structure
Cheng Peihong, Huang Shihua
J. Semicond.  2008, 29(1): 110-115
Abstract PDF

The energy levels of a Ge/Si quantum well were obtained by solving the Schordinger equation based on the finite potential well approximation.For the quantum well structure,the characteristics of capacitance-voltage (C-V) and the distribution of carrier concentration were derived in different bias voltage regions by analytically solving Poisson’s equation.The appearance of a capacitance platform is a distinct characteristic of the C-V curve for quantum well structures,which is relative to the structure parameter of the quantum well.As the thickness of capping layer decreases,the starting capacitance of the C-V platform increases and shifts toward low reverse bias.As the doping concentration in the quantum well or the capping layer increases,a high reverse bias is needed to exhaust the carriers in the quantum well,and the platform width increases.The apparent carrier concentration distribution in the quantum well can be obtained from the C-V curve.

The energy levels of a Ge/Si quantum well were obtained by solving the Schordinger equation based on the finite potential well approximation.For the quantum well structure,the characteristics of capacitance-voltage (C-V) and the distribution of carrier concentration were derived in different bias voltage regions by analytically solving Poisson’s equation.The appearance of a capacitance platform is a distinct characteristic of the C-V curve for quantum well structures,which is relative to the structure parameter of the quantum well.As the thickness of capping layer decreases,the starting capacitance of the C-V platform increases and shifts toward low reverse bias.As the doping concentration in the quantum well or the capping layer increases,a high reverse bias is needed to exhaust the carriers in the quantum well,and the platform width increases.The apparent carrier concentration distribution in the quantum well can be obtained from the C-V curve.
PL Emission of Low-Dimensional Structures Formed by Laser Irradiation
Huang Weiqi, Wu Keyue, Xu Li, Wang Haixu, Jin Feng, Liu Shirong, Qin Zhaojian, Qin Shuijie
J. Semicond.  2008, 29(1): 116-122
Abstract PDF

Certain low-dimensional nanostructures can be formed by laser irradiation on pure silicon samples and on the SiGe alloy samples.These low-dimensional nanostructures are generated by the interaction between semiconductors and the plasma produced with laser irradiation.We studied the photoluminescence (PL) of the hole-net structure of silicon and the porous structure of SiGe where the PL intensity at 706nm and at 725nm wavelength increases significantly.It is proved that surface oxidation of these structures occurs.The effect of intensity-enhancement of the PL peaks cannot be explained by quantum confinement alone.We propose a mechanism for increasing PL emission in the above structures,in which the trap states of the interfaces between SiO2 and nanocrystal play an important role.

Certain low-dimensional nanostructures can be formed by laser irradiation on pure silicon samples and on the SiGe alloy samples.These low-dimensional nanostructures are generated by the interaction between semiconductors and the plasma produced with laser irradiation.We studied the photoluminescence (PL) of the hole-net structure of silicon and the porous structure of SiGe where the PL intensity at 706nm and at 725nm wavelength increases significantly.It is proved that surface oxidation of these structures occurs.The effect of intensity-enhancement of the PL peaks cannot be explained by quantum confinement alone.We propose a mechanism for increasing PL emission in the above structures,in which the trap states of the interfaces between SiO2 and nanocrystal play an important role.
Radial Distribution of Grown-In Oxygen Precipitates in a 300mm Nitrogen-Doped Czochralski Silicon Wafer
Tian Daxi, Ma Xiangyang, Zeng Yuheng, Yang Deren, Que Duanlin
J. Semicond.  2008, 29(1): 123-127
Abstract PDF

A ramping anneal,i.e.,the isothermal anneal at an elevated temperature of 1150℃ ramped up from a starting temperature (600~1000℃) was employed to enable the growth of the grown-in oxygen precipitates that are larger than the critical size at the starting temperature.Flourier transformation infrared spectroscopy and scanning infrared microscopy are used to measure the amount of precipitated oxygen and the oxygen precipitate density in a 300mm nitrogen-doped Czochralski silicon wafer,respectively.The grown-in oxygen precipitate density in the abnormal oxygen precipitation region (generally referred to as the P-region) is much higher than that in the vacancy-type defect region (generally referred to as the V-region).Moreover,the size distribution of grown-in oxygen precipitates in the V-region is not continuous,exhibiting large precipitates formed at high temperatures and small ones formed at low temperatures;while the grown-in oxygen precipitates in the P-region are continuously formed from high to low temperatures,thus leading to a continuous size distribution.Such results are tentatively explained in terms of the formation mechanisms for grown-in oxygen precipitates generated in the V- and P-regions.

A ramping anneal,i.e.,the isothermal anneal at an elevated temperature of 1150℃ ramped up from a starting temperature (600~1000℃) was employed to enable the growth of the grown-in oxygen precipitates that are larger than the critical size at the starting temperature.Flourier transformation infrared spectroscopy and scanning infrared microscopy are used to measure the amount of precipitated oxygen and the oxygen precipitate density in a 300mm nitrogen-doped Czochralski silicon wafer,respectively.The grown-in oxygen precipitate density in the abnormal oxygen precipitation region (generally referred to as the P-region) is much higher than that in the vacancy-type defect region (generally referred to as the V-region).Moreover,the size distribution of grown-in oxygen precipitates in the V-region is not continuous,exhibiting large precipitates formed at high temperatures and small ones formed at low temperatures;while the grown-in oxygen precipitates in the P-region are continuously formed from high to low temperatures,thus leading to a continuous size distribution.Such results are tentatively explained in terms of the formation mechanisms for grown-in oxygen precipitates generated in the V- and P-regions.
Growth of p-GaN on High-Temperature AlN Templates
Liu Ting, Zou Zeya, Wang Zhen, Zhao Hong, Zhao Wenbo, Luo Muchang, Zhou Xun, Yang Xiaobo, Liao Xiuying
J. Semicond.  2008, 29(1): 128-132
Abstract PDF

Uniformity-doping and Mg-gradual-δ-doping p-type GaN epilayers are grown on HT-AlN/sapphire templates by metalorganic chemical vapor deposition (MOCVD).Compared to those grown on GaN/sapphire templates,the Mg-gradual-δ-doping process and HT-AlN/sapphire template improve the crystal quality of p-type GaN epilayers and enhance the p-type performance.The double crystal X-ray rocking curve and the Hall measurement show a full-width at half-maximum of only 178" and the highest hole concentration of 5.78e17cm-3 for the Mg-gradual-δ-doping p-type GaN epilayers grown on HT-AlN/sapphire templates.Under the optimum ratio of Cp2Mg/TMGa,the hole concentration of the p-type GaN epilayer is improved to 8.03e17cm-3.

Uniformity-doping and Mg-gradual-δ-doping p-type GaN epilayers are grown on HT-AlN/sapphire templates by metalorganic chemical vapor deposition (MOCVD).Compared to those grown on GaN/sapphire templates,the Mg-gradual-δ-doping process and HT-AlN/sapphire template improve the crystal quality of p-type GaN epilayers and enhance the p-type performance.The double crystal X-ray rocking curve and the Hall measurement show a full-width at half-maximum of only 178" and the highest hole concentration of 5.78e17cm-3 for the Mg-gradual-δ-doping p-type GaN epilayers grown on HT-AlN/sapphire templates.Under the optimum ratio of Cp2Mg/TMGa,the hole concentration of the p-type GaN epilayer is improved to 8.03e17cm-3.
Properties of CdTe Source Prepared by Close-Spaced Sublimation in O2 Atmosphere
Zeng Guanggen, Li Bing, Zheng Jiagui, Li Yuanjie, Zhang Jingquan, Li Wei, Lei Zhi, Wu Lili, Cai Yaping, Feng Lianghuan
J. Semicond.  2008, 29(1): 133-135
Abstract PDF

We studied the structure configuration and components of CdTe sources,which are often used during the preparation of the CdTe polycrystalline films with the close-spaced sublimation method.Results show that the surface of CdTe sources that are used many times are intended to become yellow,and there are CdO powders on it.The oxide on the surface can be deoxidized by H2 at high temperatures under certain conditions,which establishes a foundation for the repetitive use of CdTe source.

We studied the structure configuration and components of CdTe sources,which are often used during the preparation of the CdTe polycrystalline films with the close-spaced sublimation method.Results show that the surface of CdTe sources that are used many times are intended to become yellow,and there are CdO powders on it.The oxide on the surface can be deoxidized by H2 at high temperatures under certain conditions,which establishes a foundation for the repetitive use of CdTe source.
Design,Fabrication,and Characterization of Dual Channel Real Space Transfer Transistors
Guo Weilian, Zhang Shilin, Liang Huilai, Qi Haitao, Mao Luhong, Niu Pingjuan, Yu Xin, Wang Wei, Wang Wenxin, Chen Hong, Zhou Junming
J. Semicond.  2008, 29(1): 136-139
Abstract PDF

By adopting a dual channel structure and a GaAs substrate,a real space transfer transistor is successfully designed and fabricated.It has the standard "Λ" shaped negative resistance I-V characteristics as well as the level and smooth valley region of a conventional RSTT.The negative resistance parameters can be varied by changing the gate voltage.For example,the PVCR varies from 2.1 to 10.6V while VGS changes from 0.6 to 1.0V.The transconductance for IP (ΔIP/ΔVGS) is 0.3mS.The parameters VP and VV,and the threshold gate voltage for negative resistance characteristics are smaller than the values reported in the literatures.This device is suitable for low dissipation power application.

By adopting a dual channel structure and a GaAs substrate,a real space transfer transistor is successfully designed and fabricated.It has the standard "Λ" shaped negative resistance I-V characteristics as well as the level and smooth valley region of a conventional RSTT.The negative resistance parameters can be varied by changing the gate voltage.For example,the PVCR varies from 2.1 to 10.6V while VGS changes from 0.6 to 1.0V.The transconductance for IP (ΔIP/ΔVGS) is 0.3mS.The parameters VP and VV,and the threshold gate voltage for negative resistance characteristics are smaller than the values reported in the literatures.This device is suitable for low dissipation power application.
Fabrication and Memory Characteristics of a New Organic Thin Film Device
Guo Peng, Ji Xin, Dong Yuanwei, Lü Yinxiang, Xu Wei
J. Semicond.  2008, 29(1): 140-143
Abstract PDF

The reversible electrical bistability of a new organic thin film device with a metal/organic/metal sandwich structure is investigated.The anode and cathode metals of the device are Ag and Al,respectively,and were fabricated by vacuum evaporation.The middle medium is 2-(hexahydropyrimidin-2-ylidene)-malononitrile (HPYM).The device,which has polar memory characteristics,can be written from a low-conductance state to a high-conductance state by a voltage pulse and can be erased by a reverse voltage.The device with a thin Al2O3 layer between base metal Al and HPYM can produce different high-conductance states through the application of different positive voltages,resulting in multilevel memory capability.The effect of different electrode combinations on conductance switching devices is studied and UV-Vis absorption spectra and Raman spectra are used to obtain information on the interfaces of the devices.

The reversible electrical bistability of a new organic thin film device with a metal/organic/metal sandwich structure is investigated.The anode and cathode metals of the device are Ag and Al,respectively,and were fabricated by vacuum evaporation.The middle medium is 2-(hexahydropyrimidin-2-ylidene)-malononitrile (HPYM).The device,which has polar memory characteristics,can be written from a low-conductance state to a high-conductance state by a voltage pulse and can be erased by a reverse voltage.The device with a thin Al2O3 layer between base metal Al and HPYM can produce different high-conductance states through the application of different positive voltages,resulting in multilevel memory capability.The effect of different electrode combinations on conductance switching devices is studied and UV-Vis absorption spectra and Raman spectra are used to obtain information on the interfaces of the devices.
A Poly-Crystalline Si Anode Microcavity Organic Light Emitting Device and Its Simplified Preparation Process Flow
Li Yang, Meng Zhiguo, Wu Chunya, Man Wong, Hoi Sing Kwok, Zhang Fang, Xiong Shaozhen
J. Semicond.  2008, 29(1): 144-148
Abstract PDF

The preparation of Boron-doped solution-based metal induced crystallized poly-Si is introduced and its electrical and optical characteristics are studied.P+-MIC poly-Si thin film has good electrical characteristics and optical characteristics including high reflection and transmission and very low absorption within red light region.As a result,we used it as an OLED electrode.The maximum luminance efficiency of the device with the poly-Si anode is 5.88cd/A,57% higher than that of the OLED with the ITO anode.Systemization of the relatively high reflectivity P+-poly-Si anode with the very high reflectivity Al cathode forms a micro-cavity structure with a certain Q to improve the efficiency of OLED fabricated on it.So,a homochromy display device with high EL intensity and high saturation performance can be realized.The significance of this study and design rests with:Using P+-poly-Si,which is the same material as the active layer and source and drain electrodes of the coplanar drive TFT,as the anode of MOLED in place of ITO,which not only develops high performance MOLED,but also greatly simplifies the preparation process flow.Consequently,a simple 4-mask AMOLED panel preparation process is formed.

The preparation of Boron-doped solution-based metal induced crystallized poly-Si is introduced and its electrical and optical characteristics are studied.P+-MIC poly-Si thin film has good electrical characteristics and optical characteristics including high reflection and transmission and very low absorption within red light region.As a result,we used it as an OLED electrode.The maximum luminance efficiency of the device with the poly-Si anode is 5.88cd/A,57% higher than that of the OLED with the ITO anode.Systemization of the relatively high reflectivity P+-poly-Si anode with the very high reflectivity Al cathode forms a micro-cavity structure with a certain Q to improve the efficiency of OLED fabricated on it.So,a homochromy display device with high EL intensity and high saturation performance can be realized.The significance of this study and design rests with:Using P+-poly-Si,which is the same material as the active layer and source and drain electrodes of the coplanar drive TFT,as the anode of MOLED in place of ITO,which not only develops high performance MOLED,but also greatly simplifies the preparation process flow.Consequently,a simple 4-mask AMOLED panel preparation process is formed.
A Novel Back-Gate Kink Effect in SOI MOSFETs During Ionizing Irradiation
Liu Jie, Zhou Jicheng, Luo Hongwei, Kong Xuedong, En Yunfei, Shi Qian, He Yujuan, Lin Li
J. Semicond.  2008, 29(1): 149-152
Abstract PDF

Total dose irradiation effects of partially depleted SOI MOSFETs are studied under 10keV X-ray exposure.Results show that the front-gate characteristics do not change significantly during irradiation.An anomalous kink is observed in the back-gate logarithmic curve of both nMOS and pMOS,which is attributed to charged traps at the buried oxide/top silicon (BOX/SOI) interface during irradiation.Two-dimensional numerical simulation using MEDICI supports this conclusion.

Total dose irradiation effects of partially depleted SOI MOSFETs are studied under 10keV X-ray exposure.Results show that the front-gate characteristics do not change significantly during irradiation.An anomalous kink is observed in the back-gate logarithmic curve of both nMOS and pMOS,which is attributed to charged traps at the buried oxide/top silicon (BOX/SOI) interface during irradiation.Two-dimensional numerical simulation using MEDICI supports this conclusion.
Hydrogen Sensors Based on AlGaN/GaN Back-to-Back Schottky Diodes
Wang Xinhua, Wang Xiaoliang, Feng Chun, Ran Junxue, Xiao Hongling, Yang Cuibai, Wang Baozhu, Wang Junxi
J. Semicond.  2008, 29(1): 153-156
Abstract PDF

Hydrogen sensors based on AlGaN/GaN back-to-back Schottky diodes have been produced.Platinum is sputtered on the surface of the sample.The response of the device to 10% H2 in N2 is measured at 25~100℃.The oxygen in the air has great influence on the current of the device.Finally,the variation of the Schottky barrier height induced by the hydrogen is calculated.

Hydrogen sensors based on AlGaN/GaN back-to-back Schottky diodes have been produced.Platinum is sputtered on the surface of the sample.The response of the device to 10% H2 in N2 is measured at 25~100℃.The oxygen in the air has great influence on the current of the device.Finally,the variation of the Schottky barrier height induced by the hydrogen is calculated.
Thermally Induced Packaging Effect on the Resonant Frequencies of a Fixed-Fixed Beam
Li Ming, Song Jing, Huang Qing’an, Tang Jieying
J. Semicond.  2008, 29(1): 157-162
Abstract PDF

To characterize the effect of deformation of die-bonding packages on the performance of MEMS devices,a laser scanning vibrometer was used,based on the theory of vibration analysis and signal processing.Because it is a commonly used structure in MEMS design,a surface micromachined polysilicon fixed-fixed beam was chosen.Its resonant frequencies from the 1st to the 3rd order were recorded before and after die bonding and compared to FEM simulations.The results suggest that the thermo-mechanical coupling deformation in the multilayer packaging structure affects the performance of MEMS device remarkably,and the resonant frequencies shift of the beam are more than 15%~30%.Therefore,it is possible to include the package effect in the primary design circle of MEMS devices,which may enhance the device performance and shorten the primary design cycle.

To characterize the effect of deformation of die-bonding packages on the performance of MEMS devices,a laser scanning vibrometer was used,based on the theory of vibration analysis and signal processing.Because it is a commonly used structure in MEMS design,a surface micromachined polysilicon fixed-fixed beam was chosen.Its resonant frequencies from the 1st to the 3rd order were recorded before and after die bonding and compared to FEM simulations.The results suggest that the thermo-mechanical coupling deformation in the multilayer packaging structure affects the performance of MEMS device remarkably,and the resonant frequencies shift of the beam are more than 15%~30%.Therefore,it is possible to include the package effect in the primary design circle of MEMS devices,which may enhance the device performance and shorten the primary design cycle.
Analysis of Pull-In Voltage of RF MEMS Switches
Dong Qiaohua, Liao Xiaoping, Huang Qing’an, Huang Jianqiu
J. Semicond.  2008, 29(1): 163-167
Abstract PDF

The pull-in voltage of RF MEMS switches at different actuations is presented.When the actuation voltage is a pulse voltage,the movement of the switch beam is in a vibration state rather than quasi-static,so the pull-in voltage is different from the quasi-static condition and is called dynamic pull-in voltage.It is about 92% of the quasi-static pull-in voltage.Following the simple formula of the spring coefficient of a beam and the exact formula of the capacitor for the switch,the quasi-static and dynamic pull-in voltages of the clamped-clamped beam switch on CPW are analyzed,and the damping effect is also included.The damping reduces the difference between the two kinds of pull-in voltages.Finally,the influence of the RF input power on the pull-in voltage is analyzed.The input power decreases the pull-in voltage,reducing the pull-in voltage to zero at a certain power,and then making the switch self-actuate.

The pull-in voltage of RF MEMS switches at different actuations is presented.When the actuation voltage is a pulse voltage,the movement of the switch beam is in a vibration state rather than quasi-static,so the pull-in voltage is different from the quasi-static condition and is called dynamic pull-in voltage.It is about 92% of the quasi-static pull-in voltage.Following the simple formula of the spring coefficient of a beam and the exact formula of the capacitor for the switch,the quasi-static and dynamic pull-in voltages of the clamped-clamped beam switch on CPW are analyzed,and the damping effect is also included.The damping reduces the difference between the two kinds of pull-in voltages.Finally,the influence of the RF input power on the pull-in voltage is analyzed.The input power decreases the pull-in voltage,reducing the pull-in voltage to zero at a certain power,and then making the switch self-actuate.
Micro-Sized SnAg Solder Bumping Technology and Bonding Reliability
Lin Xiaoqin, Zhu Dapeng, Luo Le
J. Semicond.  2008, 29(1): 168-173
Abstract PDF

Experiments were carried out to investigate an area-array SnAg alloy electroplating solder bumping process with a bump size of less than 100μm.Sn-3.0Ag solder bumps with smooth and shiny surfaces,uniform distribution of Ag atoms,the height uniformity within the chip,and over Φ100mm wafer about 2.03% and 5.12% were fabricated.The intermetallic compound and micro-voids at the SnAg/Cu interface as a function of the reflow times and their effects on the bonding reliability of solder bumps were studied.The scalloped Cu6Sn5 phase grew by a ripening process during multi-reflow.Volume shrinkage during phase transformation was believed to be the main reason for the formation of voids.The average shear strength of solder bumps increased as the reflow time increased.The combination of SnAg on TiW/Cu UBM was reliable under multi-reflow.Voids showed no significant impacts on the solder bonds in this study.Voids at the layered Cu6Sn5/Cu interface would be a threat to the reliability of solder bumps.

Experiments were carried out to investigate an area-array SnAg alloy electroplating solder bumping process with a bump size of less than 100μm.Sn-3.0Ag solder bumps with smooth and shiny surfaces,uniform distribution of Ag atoms,the height uniformity within the chip,and over Φ100mm wafer about 2.03% and 5.12% were fabricated.The intermetallic compound and micro-voids at the SnAg/Cu interface as a function of the reflow times and their effects on the bonding reliability of solder bumps were studied.The scalloped Cu6Sn5 phase grew by a ripening process during multi-reflow.Volume shrinkage during phase transformation was believed to be the main reason for the formation of voids.The average shear strength of solder bumps increased as the reflow time increased.The combination of SnAg on TiW/Cu UBM was reliable under multi-reflow.Voids showed no significant impacts on the solder bonds in this study.Voids at the layered Cu6Sn5/Cu interface would be a threat to the reliability of solder bumps.
Electromigration of Cu-Ni/Solder/Ni-Cu Structures
Zhang Jinsong, Xi Hongjia, Wu Yiping, Wu Fengshun
J. Semicond.  2008, 29(1): 174-178
Abstract PDF

We investigated the electromigration mechanisms of Cu-Ni/solder/Ni-Cu structures.An electromigration process was observed when the applied average current density (0.4e4A/cm2) was lower than the threshold value for electromigration (1.0e4A/cm2).This was attributed to the maximum current density (5.83e4A/cm2) being much higher than the threshold value at the cathode area due to effects of current crowding.Because forced-convection heat transfer was introduced,the atoms’ thermal migration maximum was suppressed and did not disturb electromigration in the propagation stage.The electromigration force was dominant in this stage.In the quick-failure stage,atomic motion was driven by the cooperation of thermal migration and electromigration,which was generated by local temperature and the atoms thermal migration increasing rapidly and significantly.

We investigated the electromigration mechanisms of Cu-Ni/solder/Ni-Cu structures.An electromigration process was observed when the applied average current density (0.4e4A/cm2) was lower than the threshold value for electromigration (1.0e4A/cm2).This was attributed to the maximum current density (5.83e4A/cm2) being much higher than the threshold value at the cathode area due to effects of current crowding.Because forced-convection heat transfer was introduced,the atoms’ thermal migration maximum was suppressed and did not disturb electromigration in the propagation stage.The electromigration force was dominant in this stage.In the quick-failure stage,atomic motion was driven by the cooperation of thermal migration and electromigration,which was generated by local temperature and the atoms thermal migration increasing rapidly and significantly.
Intermediate Layer Bonding for Silicon and Glass Based on UV Adhesive
Cheng Wenjin, Tang Zirong, Liao Guanglan, Shi Tielin, Lin Xiaohui, Peng Ping
J. Semicond.  2008, 29(1): 179-182
Abstract PDF

Taking advantage of the transparency of glass and the maturity of UV curing technology,an intermediate layer bonding process with ultraviolet curable adhesive was investigated to bond silicon wafer to glass substrate.Following the spin-coating of UV-curable adhesive onto the wafer,the silicon wafer and glass substrate were bonded under UV light with a wavelength of 365nm.Experimental results demonstrate that the UV curing approach can be applied in the silicon-glass intermediate layer bonding.The bonding strength can reach over 26MPa and the thickness of the intermediate layer is about 5~6μm.The process is effective,simple,and low cost,and it will have potential applications in low-temperature microelectronics packaging.

Taking advantage of the transparency of glass and the maturity of UV curing technology,an intermediate layer bonding process with ultraviolet curable adhesive was investigated to bond silicon wafer to glass substrate.Following the spin-coating of UV-curable adhesive onto the wafer,the silicon wafer and glass substrate were bonded under UV light with a wavelength of 365nm.Experimental results demonstrate that the UV curing approach can be applied in the silicon-glass intermediate layer bonding.The bonding strength can reach over 26MPa and the thickness of the intermediate layer is about 5~6μm.The process is effective,simple,and low cost,and it will have potential applications in low-temperature microelectronics packaging.
A Metropolis Monte Carlo Simulation Approach for Anisotropic Wet Etching and Its Applications
Zhu Peng, Xing Yan, Yi Hong, Tang Wencheng
J. Semicond.  2008, 29(1): 183-188
Abstract PDF

A simulation model based on Metropolis Monte Carlo for anisotropic etching is presented.The step flow model of kink propagation is introduced in the modeling process of the simulation.For the calculation of the transaction probability of the Monte Carlo method,the removal probability function is set forth by using the nearest-neighbor bond-counting model.The simulation is carried out on different vicinal surfaces to verify the efficiency of the model.Through understanding the kink propagation,the velocity of high Miller-index facets can be explained.Compared with reported CA and other Monte Carlo methods,this model shows higher efficiency and accuracy in simulation.Finally,compensation for convex corners of the micro accelerometer is performed,and the visualization result of simulation agrees well with the experimental results.

A simulation model based on Metropolis Monte Carlo for anisotropic etching is presented.The step flow model of kink propagation is introduced in the modeling process of the simulation.For the calculation of the transaction probability of the Monte Carlo method,the removal probability function is set forth by using the nearest-neighbor bond-counting model.The simulation is carried out on different vicinal surfaces to verify the efficiency of the model.Through understanding the kink propagation,the velocity of high Miller-index facets can be explained.Compared with reported CA and other Monte Carlo methods,this model shows higher efficiency and accuracy in simulation.Finally,compensation for convex corners of the micro accelerometer is performed,and the visualization result of simulation agrees well with the experimental results.