We demonstrate the ability of a combined scanning electron microscope and cathodoluminescence (CL) spectral mapping system to provide important spatially resolved information. The degree of inhomogeneity in spectral output across a multi-quantum well sample is measured using the SEM-CL system as well as measuring the efficiency roll-off with increasing carrier concentration. The effects of low energy electron beam modification on the InGaN/GaN multi quantum wells have also been characterized.

In order to determine the environmental effects on the luminescence properties of a phosphor layer for high-power light emitting diodes, a high humidity and temperature test (85 ℃/85%RH) and a thermal aging test (85 ℃) were performed on silicone/YAG phosphor composites. The luminescence properties of silicone/phosphor composites are monitored by a fluorescence spectrometer. The results show that high temperature could result in an increase in conversion efficiency of composites during the early aging stage and red shift of YAG phosphor; and high humidity could result in a significant decrease in conversion efficiency of composites while having a small influence upon the optimal excitation wavelength of the YAG phosphor.

The nitride phosphor Sr₂Si₅N₈:Eu²⁺ was synthesized by the high temperature solid-state method. The properties of Sr₂Si₅N₈:Eu²⁺ were discussed by X-ray diffraction (XRD) scanning electron microscope (SEM) and spectra analysis. The XRD pattern shows that the single phase produces when strontium nitride is a bit excessive. The SEM photo implies that the excessive strontium nitride works as a flux in the reaction system. The position of emission peak is also located at about 612 nm as strontium nitride is excessive. The luminescent intensity of the phosphor adding excessive strontium nitride is higher than that of the phosphor introducing stoichiometric strontium nitride. The optimized content of nitride strontium was 2.05 mol/mol for the obtained phosphor with excellent properties.

The physical properties and photoelectrochemical characterization of aluminium doped hematite α-Fe₂O₃, synthesized by spray pyrolysis, have been investigated in regard to solar energy conversion. Stable Al-doped iron (III) oxide thin films synthesized by a spray pyrolysis technique reveals an oxygen deficiency, and the oxide exhibits n-type conductivity confirmed by anodic photocurrent generation. The preparative parameters have been optimized to obtain good quality thin films which are uniform and well adherent to the substrate. The deposited iron oxide thin films show the single hematite phase with polycrystalline rhombohedral crystal structure with crystallite size 20–40 nm. Optical analysis enabled to point out the increase in direct band-gap energy from 2.2 to 2.25 eV with doping concentration which is attributed to a blue shift. The dielectric constant and dielectric loss are studied as a function of frequency. To understand the conduction mechanism in the films, AC conductivity is measured. The conduction occurs by small polaron hopping through mixed valences Fe^2+/3+ with an electron mobility 300 K of 1.08 cm²/(V.s). The α-Fe₂O₃ exhibits long term chemical stability in neutral solution and has been characterized photoelectrochemically to assess its activity as a photoanode for various electrolytes using white light to obtain I–V characteristics. The Al-doped hematite exhibited a higher photocurrent response when compared with undoped films achieving a power conversion efficiency of 2.37% at 10 at% Al:Fe₂O₃ thin films along with fill factor 0.38 in NaOH electrolyte. The flat band potential V_fb(-0.87 V_SCE) is determined by extrapolating the linear part to C^-2 = 0 and the slope of the Mott-Schottky plot.

As anti-reflecting thin films and transparent electrodes of solar cells, indium tin oxide (ITO) thin films were prepared on glass substrates by DC magnetron sputtering process. The main sputtering conditions were sputtering power, substrate temperature and work pressure. The influence of the above sputtering conditions on the transmittance and conductivity of the deposited ITO films was investigated. The experimental results show that, the transmittance and the resistivity decrease as the sputtering power increases from 30 to 90 W. When the substrate temperature increases from 25 to 150 ℃, the transmittance increases slightly whereas the resistivity decreases. As the work pressure increases from 0.4 to 2.0 Pa, the transmittance decreases and the resistivity increases. When the sputtering power, substrate temperature and work pressure are 30 W, 150 ℃, 0.4 Pa respectively, the ITO thin films exhibit good electrical and optical properties, with resistivity below 10^-4Ω·cm and the transmittance in the visible wave band beyond 80%. Therefore, the ITO thin films are suitable as transparent electrodes of solar cells.

Growth rate has a direct impact on the productivity of nitride LED production. Atmospheric pressure growth of GaN with a growth rate as high as 10 μm/h and also Al_0.1Ga_0.9N growth of 1 μm/h by using 4 inch by 11 production scale MOVPE are described. XRD of (002) and (102) direction was 200 arcsec and 250 arcsec, respectively. Impact of the growth rate on productivity is discussed.

Fluorescent-SiC (f-SiC), which contains donor and acceptor impurities with optimum concentrations, has high conversion efficiency from NUV to visible light caused by donor-acceptor-pair (DAP) recombination. This material can be used as a substrate for a near UV light-emitting diode (LED) stack, and leads to monolithic white LED device with suitable spectral property for general lighting applications. In this paper, we describe basic technologies of the white LED, such as optical properties of f-SiC substrate, and epitaxial growth of NUV stack on the f-SiC substrate.

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range (–55 to 150 ℃). An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.

In most of the total dose radiation models, the drift of the threshold voltage and the degradation of the carrier mobility were only studied when the bulk potential is zero. However, the measured data indicate that the total dose effect is closely related to the bulk potential. In order to model the influence of the bulk potential on the total dose effect, we proposed a macro model. The change of the threshold voltage, carrier mobility and leakage current with different bulk potentials were all modeled in this model, and the model is well verified by the measured data based on the 0.35 μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences, especially the part of the leakage current.

A new partial-SOI (PSOI) high voltage device structure named CNCI PSOI (complementary n⁺-charge islands PSOI) is proposed. CNCI PSOI is characterized by equidistant high concentration n⁺-regions on the top and bottom interfaces of a dielectric buried layer of a PSOI device. When a high voltage is applied to the device, complementary holes and electron islands are formed on the two n⁺-regions on the top and bottom interfaces, therefore effectively enhancing the electric field of the dielectric buried layer (E_I) and increasing the breakdown voltage (BV), alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CNCI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. BV and E_I of the CNCI PSOI LDMOS increase to 591 V and 512 V/μm from 216 V and 81.4 V/μm of the conventional PSOI with a lower SHE, respectively. The influence of structure parameters on the device characteristics is analyzed for the proposed device in detail.

Due to their long lifetime and high efficacy, light emitting diodes have the potential to revolutionize the illumination industry. However, self heat and high environmental temperature which will lead to increased junction temperature and degradation due to electrical overstress can shorten the life of the light emitting diode. In this research, a methodology to investigate the degradation of the LED emitter has been proposed. The epoxy lens of the emitter can be modelled using simplified Eyring methods whereas an equation has been proposed for describing the degradation of the LED emitters.

This paper provides an analytical approach to determine the optimum pitch by utilizing a thermal resistance network, under the assumption of constant luminous efficiency. This work allows an LED array design which is mounted on a printed circuit board (PCB) attached with a heat sink subject to the natural convection cooling. Being validated by finite element (FE) models, the current approach can be shown as an effective method for the determination of optimal component spacing in an LED array assembly for SSL.

This paper designs a 3 × 3 light emitting diode (LED) array with a total power of 9 W, presents a thermal analysis of plate fin, in-line and staggered pin fin heat sinks for a high power LED lighting system, and develops a 3D one-fourth finite element (FE) model to predict the system temperature distribution. Three kinds of heat sinks are compared under the same conditions. It is found that LED chip junction temperature is 48.978 ℃ when the fins of heat sink are aligned alternately.

A new type application specific light emitting diode (LED) package (ASLP) with freeform polycarbonate lens for street lighting is developed, whose manufacturing processes are compatible with a typical LED packaging process. The reliability test methods and failure criterions from different vendors are reviewed and compared. It is found that test methods and failure criterions are quite different. The rapid reliability assessment standards are urgently needed for the LED industry. 85 ℃/85 RH with 700 mA is used to test our LED modules with three other vendors for 1000 h, showing no visible degradation in optical performance for our modules, with two other vendors showing significant degradation. Some failure analysis methods such as C-SAM, Nano X-ray CT and optical microscope are used for LED packages. Some failure mechanisms such as delaminations and cracks are detected in the LED packages after the accelerated reliability testing. The finite element simulation method is helpful for the failure analysis and design of the reliability of the LED packaging. One example is used to show one currently used module in industry is vulnerable and may not easily pass the harsh thermal cycle testing.

Recently, the high-brightness LEDs have begun to be designed for illumination application. The increased electrical currents used to drive LEDs lead to thermal issues. Thermal management for LED module is a key design parameter as high operation temperature directly affects their maximum light output, quality, reliability and life time. In this review, only passive thermal solutions used on LED module will be studied. Moreover, new thermal interface materials and passive thermal solutions applied on electronic equipments are discussed which have high potential to enhance the thermal performance of LED Module.

This paper summarizes different kinds of heat sinks on the market for high power LED lamps. Analysis is made on the thermal model of LED, PCB and heat sink separately with a simplified mode provided. Two examples of simulation are illustrated as a demonstration for the thermal simulation as guidance for LED lamp design.

In order to improve the light efficiency of the conventional GaN-based light-emitting diodes (LEDs), the indium tin oxide (ITO) film is introduced as the current spreading layer and the light anti-reflecting layer on the p-GaN surface. There is a big problem with the ITO thin film's corrosion during the electrode preparation. In this paper, at least, the edge of the ITO film was lateral corroded 3.5μm width, i.e. 6.43%–1/3 of ITO film's area. An optimized simple process, i.e. inductively couple plasma (ICP), was introduced to solve this problem. The ICP process not only prevented the ITO film from lateral corrosion, but also improved the LED's light intensity and device performance. The edge of the ITO film by ICP dry etching is steep, and the areas of ITO film are whole. Compared with the chip by wet etching, the areas of light emission increase by 6.43% at least and the chip’s lop values increase by 45.9% at most.

We packaged a series of high power white LEDs by covering the blue LED chips with yellow phosphor, red phosphor and the two phosphors mixed by appropriate mass ratio, respectively, and discussed the excitation and emission spectrum of yellow phosphor and red phosphor and the characteristics of the LEDs. We found that the luminous efficacy of the white LEDs covered with the two phosphors mixed by appropriate mass ratio was lower than that of the white LEDs covered with yellow phosphor, but the color rendering index was improved observably.

The path of photons in the thin film (TF) light emitting diode (LED) was analyzed. The reflectivity of reflector in AlGaInP TF LED with and without the AlGaInP layer was contrasted. The absorption of the AlGaInP layer was analyzed and then the light extraction was calculated and shown in figure. The TF AlGaInP LED with 8 μm and 0.6 μm GaP was fabricated. At the driving current of 20 mA, the light output power of the latter is 33% higher. For the 0.6 μm GaP LED, the etching of heavily doped GaP except the ohmic contact dot area is advised. The design and optimizing of current spreading between the n-type electrode and the p-type ohmic contact dot need further research.

AlGaN photoconductive ultraviolet detectors are fabricated to study their time response characteristics. Persistent photoconductivity, a deterring factor for the detector response time, is found to be strongly related to the grain boundary density in AlGaN epilayers. By improving the crystal-nuclei coalescence process in metal organic vapor phase epitaxy, the grain-boundary density can be reduced, resulting in an-order-of-magnitude decrease in response time.

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter (ADC) is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self-calibrated. Targeted for better linearity and lower noise, an improved digital-to-analog converter capacitor array layout strategy is presented, and a low kick-back noise latch is proposed. The chip was fabricated by using 0.18 μm 1P6M CMOS technology. The ADC achieves 61.8 dB SNDR and dissipates 455 nW only, resulting in a figure of merit of 220 fJ/conversion-step. The ADC core occupies an active area of only 674 × 639 μ m².

A 12-Bit 40-MS/s pipelined analog-to-digital converter (ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opamp-sharing and low-power opamps for low dissipation and low cost, designed in 0.13-μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise-and-distortion ratio, and –75.5-dB of total harmonic distortion (the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.

A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13-μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.

This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audio-band sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the challenges associated with continuous-time design. Measurement results show that the peak SNR of this ADC reaches 100 dB and the total power consumption is less than 30 mW.

Au/cellulose-PEPC/Au surface-type humidity sensors were fabricated by drop-casting cellulose and poly-N-epoxypropylcarbazole (PEPC) blend thin films. A blend of 2wt% of each cellulose and PEPC in benzol was used for the deposition of humidity sensing films. Blend films were deposited on glass substrates with preliminary deposited surface-type gold electrodes. Films of different thicknesses of cellulose and PEPC composite were deposited by drop-casting technique. A change in electrical resistance and capacitance of the fabricated devices was observed by increasing the relative humidity in the range of 0–95% RH. It was observed that the capacitances of the sensors increase, while their resistances decrease with increasing the relative humidity. The sensors were connected to op-amp square wave oscillators. It was observed that with increasing the relative humidity, the oscillator's frequencies were also increased in the range of 4.2–12.0 kHz for 65 μm thick film sample, 4.1–9.0 kHz for 88 μm thick film sample, and 4.2–9.0 kHz for 210 μm sample. Effects of film thickness on the oscillator's frequency with respect to humidity were also investigated. This polymer humidity sensor controlled oscillator can be used for short-range and long-range remote systems at environmental monitoring and assessment of the humidity level.

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μ m CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

This paper presents a systematic multivariate process capability index (MPCI) method, which may provide references for assuring and improving process quality levels while achieving an overall evaluation of process quality. The system method includes a spatial MPCI model for multivariate normal distribution data, MPCI model based on factor weight for multivariate no-normal distribution application, and MPCI model based on yield for yield application. At last, examples for calculating MPCI are given, and the experimental results show that this systematic method is effective and practical.