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Volume 34, Issue 10, Oct 2013
SEMICONDUCTOR PHYSICS
Transverse Stark effect in the optical absorption in a square semiconducting quantum wire
Sheng Wang, Yun Kang, Chunjie Han
J. Semicond.  2013, 34(10): 102001  doi: 10.1088/1674-4926/34/10/102001

The ground and few excited states of the electrons confined in a square GaAs quantum wire (QW) subjected to an external transverse electric field are investigated using the finite difference method within the effective-mass approximation. When the transverse electric field is applied along a side of the square quantum wire, the calculation of the eigenstates of the quantum wire has an exactly solvable problem whose solutions involve the linear combinations of two independent Airy functions. Compared with the exact analytical results using Airy functions, the results obtained by the use of the finite difference method in terms of the eigenstates of the particle in the QW are in excellent agreement. Subsequently, it is considered that the eigenstates of the particle depend on the orientations of the electric field with respect to the center axis of the QW. It is interesting that the peak value of the energy is found for the field directed along the diagonal in the QW, which can lead to a large energy shift. Meanwhile, dependence of the optical absorption phenomenon in the square QW on the optical field and applied electric field is investigated. It is shown that the optical absorption spectrum depends highly upon the polarization of the optical field and the applied electric field intensities and orientations.

The ground and few excited states of the electrons confined in a square GaAs quantum wire (QW) subjected to an external transverse electric field are investigated using the finite difference method within the effective-mass approximation. When the transverse electric field is applied along a side of the square quantum wire, the calculation of the eigenstates of the quantum wire has an exactly solvable problem whose solutions involve the linear combinations of two independent Airy functions. Compared with the exact analytical results using Airy functions, the results obtained by the use of the finite difference method in terms of the eigenstates of the particle in the QW are in excellent agreement. Subsequently, it is considered that the eigenstates of the particle depend on the orientations of the electric field with respect to the center axis of the QW. It is interesting that the peak value of the energy is found for the field directed along the diagonal in the QW, which can lead to a large energy shift. Meanwhile, dependence of the optical absorption phenomenon in the square QW on the optical field and applied electric field is investigated. It is shown that the optical absorption spectrum depends highly upon the polarization of the optical field and the applied electric field intensities and orientations.
SEMICONDUCTOR MATERIALS
The effect of solution concentration on the physical and electrochemical properties of vanadium oxide films deposited by spray pyrolysis
M. Mousavi, A. Kompany, N. Shahtahmasebi, M.M. Bagheri-Mohagheghi
J. Semicond.  2013, 34(10): 103001  doi: 10.1088/1674-4926/34/10/103001

Vanadium oxide thin films were prepared on glass substrates by using the spray pyrolysis technique. The effect of solution concentration (0.1 M, 0.2 M and 0.3 M) on the nanostructural, electrical, optical, and electrochromic properties of deposited films were investigated using X-ray diffraction, scanning electron microscopy, UV-vis spectroscopy, and cyclic volta-metrics. The X-ray diffraction shows that only the sample at 0.1 M has a single β-V2O5 phase and the others have mixed phases of vanadium oxide. The lowest sheet resistance was obtained for the samples prepared at 0.3 M solution. It was also found that the optical transparency of the samples changes from 70% to 35% and the optical band gap of the samples was in the range of 2.20 to 2.41 eV, depending on the morality of solution. The cycle voltammogram shows that the sample prepared at 0.3 M has one-step electerochoromic but the other samples have two-step electerochoromic. The results show a correlation between the cycle voltammogram and the physical properties of the films.

Vanadium oxide thin films were prepared on glass substrates by using the spray pyrolysis technique. The effect of solution concentration (0.1 M, 0.2 M and 0.3 M) on the nanostructural, electrical, optical, and electrochromic properties of deposited films were investigated using X-ray diffraction, scanning electron microscopy, UV-vis spectroscopy, and cyclic volta-metrics. The X-ray diffraction shows that only the sample at 0.1 M has a single β-V2O5 phase and the others have mixed phases of vanadium oxide. The lowest sheet resistance was obtained for the samples prepared at 0.3 M solution. It was also found that the optical transparency of the samples changes from 70% to 35% and the optical band gap of the samples was in the range of 2.20 to 2.41 eV, depending on the morality of solution. The cycle voltammogram shows that the sample prepared at 0.3 M has one-step electerochoromic but the other samples have two-step electerochoromic. The results show a correlation between the cycle voltammogram and the physical properties of the films.
The influence of monomer concentration on the optical properties of electrochemically synthesized polypyrrole thin films
J.V. Thombare, M.C. Rath, S.H. Han, V.J. Fulari
J. Semicond.  2013, 34(10): 103002  doi: 10.1088/1674-4926/34/10/103002

Polypyrrole (PPy) thin films were deposited on stainless steel and ITO coated glass substrate at a constant deposition potential of 0.8 V versus saturated calomel electrode (SCE) by using the electrochemical polymerization method. The PPy thin films were deposited at room temperature at various monomer concentrations ranging from 0.1 M to 0.3 M pyrrole. The structural and optical properties of the polypyrrole thin films were investigated using an X-ray diffractometer (XRD), FTIR spectroscopy, scanning electron microscopy (SEM), and ultraviolet-visible (UV-vis) spectroscopy. The XRD results show that polypyrrole thin films have a semi crystalline structure. Higher monomer concentration results in a slight increase of crystallinity. The polypyrrole thin films deposited at higher monomer concentration exhibit high visible absorbance. The refractive indexes of the polypyrrole thin films are found to be in the range of 1 to 1.3 and vary with monomer concentration as well as wavelength. The extinction coefficient decreases slightly with monomer concentration. The electrochemically synthesized polypyrrole thin film shows optical band gap energy of 2.14 eV.

Polypyrrole (PPy) thin films were deposited on stainless steel and ITO coated glass substrate at a constant deposition potential of 0.8 V versus saturated calomel electrode (SCE) by using the electrochemical polymerization method. The PPy thin films were deposited at room temperature at various monomer concentrations ranging from 0.1 M to 0.3 M pyrrole. The structural and optical properties of the polypyrrole thin films were investigated using an X-ray diffractometer (XRD), FTIR spectroscopy, scanning electron microscopy (SEM), and ultraviolet-visible (UV-vis) spectroscopy. The XRD results show that polypyrrole thin films have a semi crystalline structure. Higher monomer concentration results in a slight increase of crystallinity. The polypyrrole thin films deposited at higher monomer concentration exhibit high visible absorbance. The refractive indexes of the polypyrrole thin films are found to be in the range of 1 to 1.3 and vary with monomer concentration as well as wavelength. The extinction coefficient decreases slightly with monomer concentration. The electrochemically synthesized polypyrrole thin film shows optical band gap energy of 2.14 eV.
The optical-electrical properties of doped β-FeSi2
Wanjun Yan, Chunhong Zhang, Zhongzheng Zhang, Quan Xie, Benhua Guo, Shiyun Zhou
J. Semicond.  2013, 34(10): 103003  doi: 10.1088/1674-4926/34/10/103003

By using the pseudo-potential plane-wave method of first principles based on the density function theory, the geometrical, electronic structures and optical properties of FeSi1.875M0.125 (M=B, N, Al, P) were calculated and analyzed. The calculated structural parameters depend strongly on the kinds of dopants and sites. The total energy calculations for substitution of dopants at the SiI and the SiⅡ sites revealed that Al and P prefer the SiI sites, whereas B and N prefer the SiⅡ sites. The calculations predict that B-and Al-doped β-FeSi2 show p-type conduction, while N-and P-doped show n-type. Optical property calculations show that N-doping has little influence on the complex dielectric function of β -FeSi2; B-, N-, Al-and P-doping can enhance the electronic transition, refractive index, and reflection effect in the low-energy range, and weaken the reflection effect at the max peak of reflectivity. These results can offer theoretical guidance for the design and application of optoelectronic material β -FeSi2.

By using the pseudo-potential plane-wave method of first principles based on the density function theory, the geometrical, electronic structures and optical properties of FeSi1.875M0.125 (M=B, N, Al, P) were calculated and analyzed. The calculated structural parameters depend strongly on the kinds of dopants and sites. The total energy calculations for substitution of dopants at the SiI and the SiⅡ sites revealed that Al and P prefer the SiI sites, whereas B and N prefer the SiⅡ sites. The calculations predict that B-and Al-doped β-FeSi2 show p-type conduction, while N-and P-doped show n-type. Optical property calculations show that N-doping has little influence on the complex dielectric function of β -FeSi2; B-, N-, Al-and P-doping can enhance the electronic transition, refractive index, and reflection effect in the low-energy range, and weaken the reflection effect at the max peak of reflectivity. These results can offer theoretical guidance for the design and application of optoelectronic material β -FeSi2.
The effect of the multi-period on the properties of deep-ultraviolet transparent conductive Ga2O3/ITO alternating multilayer films
Chengyang Xu, Jinliang Yan, Chao Li, Huihui Zhuang
J. Semicond.  2013, 34(10): 103004  doi: 10.1088/1674-4926/34/10/103004

Ga2O3/ITO alternating multilayer films were deposited on quartz glass substrates by magnetron sputtering. The effect of the multi-period on the structural, optical and electrical properties of Ga2O3/ITO alternating multilayer films was investigated by an X-ray diffractometer, a double beam spectrophotometer and the Hall system, respectively. A low sheet resistance of 225.5Ω/ꭐ and a high transmittance of more than 62.9% at a 300 nm wavelength were obtained for the two-period alternating multilayer film with a thickness of 72 nm.

Ga2O3/ITO alternating multilayer films were deposited on quartz glass substrates by magnetron sputtering. The effect of the multi-period on the structural, optical and electrical properties of Ga2O3/ITO alternating multilayer films was investigated by an X-ray diffractometer, a double beam spectrophotometer and the Hall system, respectively. A low sheet resistance of 225.5Ω/ꭐ and a high transmittance of more than 62.9% at a 300 nm wavelength were obtained for the two-period alternating multilayer film with a thickness of 72 nm.
Influence of co-precipitation of copper and nickel on the formation of a denuded zone in Czochralski silicon
Chuan Ji, Guangchao Zhang, Jin Xu
J. Semicond.  2013, 34(10): 103005  doi: 10.1088/1674-4926/34/10/103005

The influence of co-precipitation of copper and nickel on the formation of a denuded zone (DZ) in Czochralski silicon (Cz Si) was systematically investigated by means of etching and optical microscopy (OM). It was found that, for conventional high-low-high annealing (CFA), the DZ could be obtained in all specimens contaminated by copper and nickel co-impurity at different steps of the heat treatment, indicating that no copper precipitates or nickel precipitates were generated in the region just below the surface. However, for rapid thermal annealing (RTA)-low-high annealing, the tendency is not the same; the DZ could not be found in the specimen which was contaminated by copper and nickel contamination before the first RTA annealing. On the basis of the experimental results, it was supposed that the concentration and distribution of the vacancies generating during the RTA can influence the distribution of copper precipitation and nickel precipitation along the cross-section of Cz Si significantly, and thus influence the formation of the DZ to a great extent.

The influence of co-precipitation of copper and nickel on the formation of a denuded zone (DZ) in Czochralski silicon (Cz Si) was systematically investigated by means of etching and optical microscopy (OM). It was found that, for conventional high-low-high annealing (CFA), the DZ could be obtained in all specimens contaminated by copper and nickel co-impurity at different steps of the heat treatment, indicating that no copper precipitates or nickel precipitates were generated in the region just below the surface. However, for rapid thermal annealing (RTA)-low-high annealing, the tendency is not the same; the DZ could not be found in the specimen which was contaminated by copper and nickel contamination before the first RTA annealing. On the basis of the experimental results, it was supposed that the concentration and distribution of the vacancies generating during the RTA can influence the distribution of copper precipitation and nickel precipitation along the cross-section of Cz Si significantly, and thus influence the formation of the DZ to a great extent.
Reduced defect density in microcrystalline silicon by hydrogen plasma treatment
Jingyan Li, Xiangbo Zeng, Hao Li, Xiaobing Xie, Ping Yang, Haibo Xiao, Xiaodong Zhang, Qiming Wang
J. Semicond.  2013, 34(10): 103006  doi: 10.1088/1674-4926/34/10/103006

The effect of hydrogen plasma treatment (HPT) during the initial stage of microcrystalline silicon (μc-Si) growth on the defect density of μc-Si has been investigated. Lower absorption coefficient in the 0.8-1.0 eV indicated less defect density compared to its counterpart without HPT. The infrared spectroscopy of μc-Si with HPT shows an increase in 2040 cm-1, which reveals more Si-H in the amorphous/crystalline interfaces. We ascribe the decrease of defect density to hydrogen passivation of the dangling bonds. Improved performance of μc-Si solar cell with HPT is due to the reduced defect density.

The effect of hydrogen plasma treatment (HPT) during the initial stage of microcrystalline silicon (μc-Si) growth on the defect density of μc-Si has been investigated. Lower absorption coefficient in the 0.8-1.0 eV indicated less defect density compared to its counterpart without HPT. The infrared spectroscopy of μc-Si with HPT shows an increase in 2040 cm-1, which reveals more Si-H in the amorphous/crystalline interfaces. We ascribe the decrease of defect density to hydrogen passivation of the dangling bonds. Improved performance of μc-Si solar cell with HPT is due to the reduced defect density.
SEMICONDUCTOR DEVICES
Stability performance of optimized symmetric DG-MOSFET
K Sivasankaran, P S Mallick
J. Semicond.  2013, 34(10): 104001  doi: 10.1088/1674-4926/34/10/104001

This article presents the bias and geometry optimization procedure for the radio frequency (RF) stability performance of nanoscale symmetric double-gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs). The stability model can provide hints for optimizing the DG-MOSFET under an RF range. The device parameters are extracted for different bias and geometry conditions through numerical simulation, and the RF figures of merit such as cut-off frequency (ft) and maximum oscillation frequency (fmax), along with stability factor, are calculated for an optimized structure. The proposed structure exhibits good RF stability performance.

This article presents the bias and geometry optimization procedure for the radio frequency (RF) stability performance of nanoscale symmetric double-gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs). The stability model can provide hints for optimizing the DG-MOSFET under an RF range. The device parameters are extracted for different bias and geometry conditions through numerical simulation, and the RF figures of merit such as cut-off frequency (ft) and maximum oscillation frequency (fmax), along with stability factor, are calculated for an optimized structure. The proposed structure exhibits good RF stability performance.
Investigation of the current collapse induced in InGaN back barrier AlGaN/GaN high electron mobility transistors
Xiaojia Wan, Xiaoliang Wang, Hongling Xiao, Chun Feng, Lijuan Jiang, Shenqi Qu, Zhanguo Wang, Xun Hou
J. Semicond.  2013, 34(10): 104002  doi: 10.1088/1674-4926/34/10/104002

Current collapses were studied, which were observed in AlGaN/GaN high electron mobility transistors (HEMTs) with and without InGaN back barrier (BB) as a result of short-term bias stress. More serious drain current collapses were observed in InGaN BB AlGaN/GaN HEMTs compared with the traditional HEMTs. The results indicate that the defects and surface states induced by the InGaN BB layer may enhance the current collapse. The surface states may be the primary mechanism of the origination of current collapse in AlGaN/GaN HEMTs for short-term direct current stress.

Current collapses were studied, which were observed in AlGaN/GaN high electron mobility transistors (HEMTs) with and without InGaN back barrier (BB) as a result of short-term bias stress. More serious drain current collapses were observed in InGaN BB AlGaN/GaN HEMTs compared with the traditional HEMTs. The results indicate that the defects and surface states induced by the InGaN BB layer may enhance the current collapse. The surface states may be the primary mechanism of the origination of current collapse in AlGaN/GaN HEMTs for short-term direct current stress.
Large-signal characterization of DDR silicon IMPATTs operating in millimeter-wave and terahertz regime
Aritra Acharyya, Jit Chakraborty, Kausik Das, Subir Datta, Pritam De, Suranjana Banerjee, J.P. Banerjee
J. Semicond.  2013, 34(10): 104003  doi: 10.1088/1674-4926/34/10/104003

The authors have carried out the large-signal characterization of silicon-based double-drift region (DDR) impact avalanche transit time (IMPATT) devices designed to operate up to 0.5 THz using a large-signal simulation method developed by the authors based on non-sinusoidal voltage excitation. The effect of band-to-band tunneling as well as parasitic series resistance on the large-signal properties of DDR Si IMPATTs have also been studied at different mm-wave and THz frequencies. Large-signal simulation results show that DDR Si IMPATT is capable of delivering peak RF power of 633.69 mW with 7.95% conversion efficiency at 94 GHz for 50% voltage modulation, whereas peak RF power output and efficiency fall to 81.08 mW and 2.01% respectively at 0.5 THz for same voltage modulation. The simulation results are compared with the experimental results and are found to be in close agreement.

The authors have carried out the large-signal characterization of silicon-based double-drift region (DDR) impact avalanche transit time (IMPATT) devices designed to operate up to 0.5 THz using a large-signal simulation method developed by the authors based on non-sinusoidal voltage excitation. The effect of band-to-band tunneling as well as parasitic series resistance on the large-signal properties of DDR Si IMPATTs have also been studied at different mm-wave and THz frequencies. Large-signal simulation results show that DDR Si IMPATT is capable of delivering peak RF power of 633.69 mW with 7.95% conversion efficiency at 94 GHz for 50% voltage modulation, whereas peak RF power output and efficiency fall to 81.08 mW and 2.01% respectively at 0.5 THz for same voltage modulation. The simulation results are compared with the experimental results and are found to be in close agreement.
A 1.65 μm three-section distributed Bragg reflector (DBR) laser for CH4 gas sensors
Bin Niu, Hongyan Yu, Liqiang Yu, Daibing Zhou, Dan Lu, Lingjuan Zhao, Jiaoqing Pan, Wei Wang
J. Semicond.  2013, 34(10): 104004  doi: 10.1088/1674-4926/34/10/104004

A 1.65-μm three-section distributed Bragg reflector (DBR) laser for CH4 gas sensors is reported. The DBR laser has a wide tunable range covering the R3 and R4 methane absorption line manifolds. The wavelength tunability properties, temperature stability and laser linewidth are characterized and analyzed. Several advantages were demonstrated compared with traditional DFB lasers in harmonic detection.

A 1.65-μm three-section distributed Bragg reflector (DBR) laser for CH4 gas sensors is reported. The DBR laser has a wide tunable range covering the R3 and R4 methane absorption line manifolds. The wavelength tunability properties, temperature stability and laser linewidth are characterized and analyzed. Several advantages were demonstrated compared with traditional DFB lasers in harmonic detection.
Enhanced light extraction of InGaN LEDs with photonic crystals grown on p-GaN using selective-area epitaxy and nanospherical-lens photolithography
Linghui Zhao, Tongbo Wei, Junxi Wang, Qingfeng Yan, Yiping Zeng, Jinmin Li
J. Semicond.  2013, 34(10): 104005  doi: 10.1088/1674-4926/34/10/104005

We report a new method for the fabrication of two-dimensional photonic crystal (PhC) hole arrays to improve the light extraction of GaN-based light-emitting diodes (LEDs). The PhC structures were realized using nanospherical-lens photolithography and the selective-area epitaxy method, which ensured the electrical properties of the LEDs through leaving the p-GaN damage-free. At a current of 350 mA, the light output power of LEDs with PhC hole arrays of 450 nm and 600 nm in diameter with the same lattice period of 900 nm were enhanced by 49.3% and 72.2%, respectively, compared to LEDs without a PhC. Furthermore, the LEDs with PhC hole structures showed an obviously smaller divergent angle compared with conventional LEDs, which is consistent with the results of finite-difference time-domain simulation.

We report a new method for the fabrication of two-dimensional photonic crystal (PhC) hole arrays to improve the light extraction of GaN-based light-emitting diodes (LEDs). The PhC structures were realized using nanospherical-lens photolithography and the selective-area epitaxy method, which ensured the electrical properties of the LEDs through leaving the p-GaN damage-free. At a current of 350 mA, the light output power of LEDs with PhC hole arrays of 450 nm and 600 nm in diameter with the same lattice period of 900 nm were enhanced by 49.3% and 72.2%, respectively, compared to LEDs without a PhC. Furthermore, the LEDs with PhC hole structures showed an obviously smaller divergent angle compared with conventional LEDs, which is consistent with the results of finite-difference time-domain simulation.
A GaAs/GaInP dual junction solar cell grown by molecular beam epitaxy
Pan Dai, Shulong Lu, Lian Ji, Wei He, Lifeng Bian, Hui Yang, M. Arimochi, H. Yoshida, S. Uchida, M. Ikeda
J. Semicond.  2013, 34(10): 104006  doi: 10.1088/1674-4926/34/10/104006

We report the recent result of GaAs/GaInP dual-junction solar cells grown by all solid-state molecular-beam-epitaxy (MBE). The device structure consists of a GaIn0.48P homojunction grown epitaxially upon a GaAs homojunction, with an interconnected GaAs tunnel junction. A photovoltaic conversion efficiency of 27% under the AM1.5 globe light intensity is realized for a GaAs/GaInP dual-junction solar cell, while the efficiencies of 26% and 16.6% are reached for a GaAs bottom cell and a GaInP top cell, respectively. The energy loss mechanism of our GaAs/GaInP tandem dual-junction solar cells is discussed. It is demonstrated that the MBE-grown phosphide-containing Ⅲ-Ⅴ compound semiconductor solar cell is very promising for achieving high energy conversion efficiency.

We report the recent result of GaAs/GaInP dual-junction solar cells grown by all solid-state molecular-beam-epitaxy (MBE). The device structure consists of a GaIn0.48P homojunction grown epitaxially upon a GaAs homojunction, with an interconnected GaAs tunnel junction. A photovoltaic conversion efficiency of 27% under the AM1.5 globe light intensity is realized for a GaAs/GaInP dual-junction solar cell, while the efficiencies of 26% and 16.6% are reached for a GaAs bottom cell and a GaInP top cell, respectively. The energy loss mechanism of our GaAs/GaInP tandem dual-junction solar cells is discussed. It is demonstrated that the MBE-grown phosphide-containing Ⅲ-Ⅴ compound semiconductor solar cell is very promising for achieving high energy conversion efficiency.
An accurate simulation model for single-photon avalanche diodes including important statistical effects
Qiuyang He, Yue Xu, Feifei Zhao
J. Semicond.  2013, 34(10): 104007  doi: 10.1088/1674-4926/34/10/104007

An accurate and complete circuit simulation model for single-photon avalanche diodes (SPADs) is presented. The derived model is not only able to simulate the static DC and dynamic AC behaviors of an SPAD operating in Geiger-mode, but also can emulate the second breakdown and the forward bias behaviors. In particular, it considers important statistical effects, such as dark-counting and after-pulsing phenomena. The developed model is implemented using the Verilog-A description language and can be directly performed in commercial simulators such as Cadence Spectre. The Spectre simulation results give a very good agreement with the experimental results reported in the open literature. This model shows a high simulation accuracy and very fast simulation rate.

An accurate and complete circuit simulation model for single-photon avalanche diodes (SPADs) is presented. The derived model is not only able to simulate the static DC and dynamic AC behaviors of an SPAD operating in Geiger-mode, but also can emulate the second breakdown and the forward bias behaviors. In particular, it considers important statistical effects, such as dark-counting and after-pulsing phenomena. The developed model is implemented using the Verilog-A description language and can be directly performed in commercial simulators such as Cadence Spectre. The Spectre simulation results give a very good agreement with the experimental results reported in the open literature. This model shows a high simulation accuracy and very fast simulation rate.
Fabrication of a microstrip patch antenna integrated in low-resistance silicon wafer using a BCB dielectric
Tianxi Wang, Mei Han, Gaowei Xu, Le Luo
J. Semicond.  2013, 34(10): 104008  doi: 10.1088/1674-4926/34/10/104008

This paper demonstrates a technique for microstrip patch antenna fabrication using a benzocyclobutene (BCB) dielectric. The most distinctive feature of this method is that the antenna is integrated on a low-resistance silicon wafer, and is fully compatible with the microwave multi-chip module packaging process. Low-permittivity dielectric BCB with excellent thermal and mechanical stability is employed to enhance the performance of the antenna. The as-fabricated antenna is characterized, and the experimental results show that the antenna resonates at 14.9 GHz with a 1.67% impedance bandwidth.

This paper demonstrates a technique for microstrip patch antenna fabrication using a benzocyclobutene (BCB) dielectric. The most distinctive feature of this method is that the antenna is integrated on a low-resistance silicon wafer, and is fully compatible with the microwave multi-chip module packaging process. Low-permittivity dielectric BCB with excellent thermal and mechanical stability is employed to enhance the performance of the antenna. The as-fabricated antenna is characterized, and the experimental results show that the antenna resonates at 14.9 GHz with a 1.67% impedance bandwidth.
An integrated MEMS piezoresistive tri-axis accelerometer
Yongping Zhang, Changde He, Jiaqi Yu, Chunhui Du, Juanting Zhang, Xiujian Chou, Wendong Zhang
J. Semicond.  2013, 34(10): 104009  doi: 10.1088/1674-4926/34/10/104009

An integrated MEMS accelerometer has been designed and fabricated. The device, which is based on the piezoresistive effect, accomplishes the detection of three components of acceleration by using piezoresistors to compose three Wheatstone bridges that are sensitive to the only given orientation. The fabrication of the accelerometer is described, and the theory behind its operation developed. Experimental results on sensitivity, cross-axis-coupling degree, and linearity are presented. The sensitivity of X, Y and Z were 5.49 mV/g, 5.12 mV/g and 4.82 mV/g, respectively; the nonlinearity of X, Y and Z were 0.01%, 0.04% and 0.01%, respectively; the cross-axis-coupling factor of X axis to Y axis and Z axis are 0.119% and 2.26%; the cross-axis-coupling factor of Y axis to X axis and Z axis are 0.157% and 4.12%; the cross-axis-coupling factor of Z axis to X axis and Y axis are 0.511% and 0.938%. The measured performance indexes attain accurate vector-detection in practical applications, and even at a navigation level. In conclusion, the accelerometer is a highly integrated sensor.

An integrated MEMS accelerometer has been designed and fabricated. The device, which is based on the piezoresistive effect, accomplishes the detection of three components of acceleration by using piezoresistors to compose three Wheatstone bridges that are sensitive to the only given orientation. The fabrication of the accelerometer is described, and the theory behind its operation developed. Experimental results on sensitivity, cross-axis-coupling degree, and linearity are presented. The sensitivity of X, Y and Z were 5.49 mV/g, 5.12 mV/g and 4.82 mV/g, respectively; the nonlinearity of X, Y and Z were 0.01%, 0.04% and 0.01%, respectively; the cross-axis-coupling factor of X axis to Y axis and Z axis are 0.119% and 2.26%; the cross-axis-coupling factor of Y axis to X axis and Z axis are 0.157% and 4.12%; the cross-axis-coupling factor of Z axis to X axis and Y axis are 0.511% and 0.938%. The measured performance indexes attain accurate vector-detection in practical applications, and even at a navigation level. In conclusion, the accelerometer is a highly integrated sensor.
SEMICONDUCTOR INTEGRATED CIRCUITS
A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters
Mingyi Chen, Xiaojie Chu, Peng Yu, Jun Yan, Yin Shi
J. Semicond.  2013, 34(10): 105001  doi: 10.1088/1674-4926/34/10/105001

A fully integrated Δ Σ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network (WLAN) transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.

A fully integrated Δ Σ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network (WLAN) transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.
A novel buck/LDO dual-mode DC-DC converter for efficiency improvement
Shiquan Fan, Zhongming Xue, Hao Lu, Hui Zhao, Li Geng
J. Semicond.  2013, 34(10): 105002  doi: 10.1088/1674-4926/34/10/105002

A novel buck/LDO dual-mode (BLDM) converter using a multiplexing power MOS transistor is proposed, which adaptively switches between buck mode and LDO mode to improve conversion efficiency. The chip was fabricated in a standard 0.35 μm CMOS process. Measurement results show that the peak efficiency is 97%. For the light load operation, the efficiency is improved by 14%. The efficiency keeps higher than 82.5% for the load current of 50 mA without any complex control or extra EMI due to the normal method of pulse frequency modulation (PFM) control used for improving the light load efficiency. It does not cost much extra chip area because no additional regulator PMOS is needed. It is more suitable for noise-restricted systems and battery-powered electronic devices for when battery voltage drops because of long hours of work.

A novel buck/LDO dual-mode (BLDM) converter using a multiplexing power MOS transistor is proposed, which adaptively switches between buck mode and LDO mode to improve conversion efficiency. The chip was fabricated in a standard 0.35 μm CMOS process. Measurement results show that the peak efficiency is 97%. For the light load operation, the efficiency is improved by 14%. The efficiency keeps higher than 82.5% for the load current of 50 mA without any complex control or extra EMI due to the normal method of pulse frequency modulation (PFM) control used for improving the light load efficiency. It does not cost much extra chip area because no additional regulator PMOS is needed. It is more suitable for noise-restricted systems and battery-powered electronic devices for when battery voltage drops because of long hours of work.
A wideband large dynamic range and high linearity RF front-end for U-band mobile DTV
Rongjiang Liu, Shengyou Liu, Guiliang Guo, Xu Cheng, Yuepeng Yan
J. Semicond.  2013, 34(10): 105003  doi: 10.1088/1674-4926/34/10/105003

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier (LNA), an RF programmable gain amplifier (RFPGA) and a current communicating passive mixer. The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA. An RFPGA with five stages provides large dynamic range and fine gain resolution. A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor, and optimum linearity and symmetrical mixing is obtained at the same time. The RF front-end is implemented in a 0.25 μm CMOS process. Tests show that it achieves an ⅡP3 (third-order intercept point) of -17 dBm, a conversion gain of 39 dB, and a noise figure of 5.8 dB. The RFPGA achieves a dynamic range of -36.2 to 23.5 dB with a resolution of 0.32 dB.

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier (LNA), an RF programmable gain amplifier (RFPGA) and a current communicating passive mixer. The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA. An RFPGA with five stages provides large dynamic range and fine gain resolution. A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor, and optimum linearity and symmetrical mixing is obtained at the same time. The RF front-end is implemented in a 0.25 μm CMOS process. Tests show that it achieves an ⅡP3 (third-order intercept point) of -17 dBm, a conversion gain of 39 dB, and a noise figure of 5.8 dB. The RFPGA achieves a dynamic range of -36.2 to 23.5 dB with a resolution of 0.32 dB.
A voltage regulator system with dynamic bandwidth boosting for passive UHF RFID transponders
Jinpeng Shen, Xin'an Wang, Shan Liu, Shoucheng Li, Zhengkun Ruan
J. Semicond.  2013, 34(10): 105004  doi: 10.1088/1674-4926/34/10/105004

This paper presents a voltage regulator system for passive UHF RFID transponders, which contains a rectifier, a limiter, and a regulator. The rectifier achieves power by rectifying the incoming RF energy. Due to the huge variation of the rectified voltage, a limiter at the rectifier output is used to clamp the rectified voltage. In this paper, the design of a limiter circuit is discussed in detail, which can provide a stable limiting voltage with low sensitivity to temperature variation and process dispersion. The key aspect of the voltage regulator system is the dynamic bandwidth boosting in the regulator. By sensing the excess current that is bypassed in the limiter during periods of excess energy, the bias current as well as the bandwidth of the regulator are increased, the output supply voltage can recover quickly from line transients during the periods of no RF energy to a full blast of RF energy. This voltage regulator system is implemented in a 0.18 μm CMOS process.

This paper presents a voltage regulator system for passive UHF RFID transponders, which contains a rectifier, a limiter, and a regulator. The rectifier achieves power by rectifying the incoming RF energy. Due to the huge variation of the rectified voltage, a limiter at the rectifier output is used to clamp the rectified voltage. In this paper, the design of a limiter circuit is discussed in detail, which can provide a stable limiting voltage with low sensitivity to temperature variation and process dispersion. The key aspect of the voltage regulator system is the dynamic bandwidth boosting in the regulator. By sensing the excess current that is bypassed in the limiter during periods of excess energy, the bias current as well as the bandwidth of the regulator are increased, the output supply voltage can recover quickly from line transients during the periods of no RF energy to a full blast of RF energy. This voltage regulator system is implemented in a 0.18 μm CMOS process.
VLSI implementation of MIMO detection for 802.11n using a novel adaptive tree search algorithm
Heng Yao, Haifang Jian, Liguo Zhou, Yin Shi
J. Semicond.  2013, 34(10): 105005  doi: 10.1088/1674-4926/34/10/105005

A 4×4 64-QAM multiple-input multiple-output (MIMO) detector is presented for the application of an IEEE 802.11n wireless local area network. The detector is the implementation of a novel adaptive tree search (ATS) algorithm, and multiple ATS cores need to be instantiated to achieve the wideband requirement in the 802.11n standard. Both the ATS algorithm and the architectural considerations are explained. The latency of the detector is 0.75 μs, and the detector has a gate count of 848 k with a total of 19 parallel ATS cores. Each ATS core runs at 67 MHz. Measurement results show that compared with the floating-point ATS algorithm, the fixed-point implementation achieves a loss of 0.9 dB at a BER of 10-3.

A 4×4 64-QAM multiple-input multiple-output (MIMO) detector is presented for the application of an IEEE 802.11n wireless local area network. The detector is the implementation of a novel adaptive tree search (ATS) algorithm, and multiple ATS cores need to be instantiated to achieve the wideband requirement in the 802.11n standard. Both the ATS algorithm and the architectural considerations are explained. The latency of the detector is 0.75 μs, and the detector has a gate count of 848 k with a total of 19 parallel ATS cores. Each ATS core runs at 67 MHz. Measurement results show that compared with the floating-point ATS algorithm, the fixed-point implementation achieves a loss of 0.9 dB at a BER of 10-3.
Design of a low-power 433/915-MHz RF front-end with a current-reuse common-gate LNA
Yiou Jing, Huaxiang Lu
J. Semicond.  2013, 34(10): 105006  doi: 10.1088/1674-4926/34/10/105006

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier (LNA), current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device (SRD) applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2. Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of -24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption.

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier (LNA), current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device (SRD) applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2. Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of -24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption.
Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS
Long Cheng, Yu Zhu, Kai Zhu, Chixiao Chen, Junyan Ren
J. Semicond.  2013, 34(10): 105007  doi: 10.1088/1674-4926/34/10/105007

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm2.

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm2.
Novel bandgap-based under-voltage-lockout methods with high reliability
Yongrui Zhao, Xinquan Lai
J. Semicond.  2013, 34(10): 105008  doi: 10.1088/1674-4926/34/10/105008

Highly reliable bandgap-based under-voltage-lockout (UVLO) methods are presented in this paper. The proposed under-voltage state to signal conversion methods take full advantages of the high temperature stability characteristics and the enhancement low-voltage protection methods which protect the core circuit from error operation; moreover, a common-source stage amplifier method is introduced to expand the output voltage range. All of these methods are verified in a UVLO circuit fabricated with a 0.5 μm standard BCD process technology. The experimental result shows that the proposed bandgap method exhibits a good temperature coefficient of 20 ppm/℃, which ensures that the UVLO keeps a stable output until the under-voltage state changes. Moreover, at room temperature, the high threshold voltage VTH+ generated by the UVLO is 12.3 V with maximum drift voltage of ±80 mV, and the low threshold voltage VTH- is 9.5 V with maximum drift voltage of ±70 mV. Also, the low voltage protection method used in the circuit brings a high reliability when the supply voltage is very low.

Highly reliable bandgap-based under-voltage-lockout (UVLO) methods are presented in this paper. The proposed under-voltage state to signal conversion methods take full advantages of the high temperature stability characteristics and the enhancement low-voltage protection methods which protect the core circuit from error operation; moreover, a common-source stage amplifier method is introduced to expand the output voltage range. All of these methods are verified in a UVLO circuit fabricated with a 0.5 μm standard BCD process technology. The experimental result shows that the proposed bandgap method exhibits a good temperature coefficient of 20 ppm/℃, which ensures that the UVLO keeps a stable output until the under-voltage state changes. Moreover, at room temperature, the high threshold voltage VTH+ generated by the UVLO is 12.3 V with maximum drift voltage of ±80 mV, and the low threshold voltage VTH- is 9.5 V with maximum drift voltage of ±70 mV. Also, the low voltage protection method used in the circuit brings a high reliability when the supply voltage is very low.
A multi-channel fully differential programmable integrated circuit for neural recording application
Yun Gui, Xu Zhang, Yuan Wang, Ming Liu, Weihua Pei, Kai Liang, Suibiao Huang, Bin Li, Hongda Chen
J. Semicond.  2013, 34(10): 105009  doi: 10.1088/1674-4926/34/10/105009

A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4th-order Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77 μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.

A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4th-order Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77 μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.
A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS
Xiangyu Meng, Baoyong Chi, Haikun Jia, Lixue Kuang, Wen Jia, Zhihua Wang
J. Semicond.  2013, 34(10): 105010  doi: 10.1088/1674-4926/34/10/105010

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity (10 Ω· cm) silicon substrate is presented. The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization. The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane. The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance. The simulated S11 is less than -10 dB over 46-95 GHz, which is well matched with the measured results over the available 40-67 GHz frequency range from our measurement equipment. A maximum gain of -5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansoft HFSS simulation. Compared with the current state-of-the-art devices, the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.

A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity (10 Ω· cm) silicon substrate is presented. The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization. The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane. The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance. The simulated S11 is less than -10 dB over 46-95 GHz, which is well matched with the measured results over the available 40-67 GHz frequency range from our measurement equipment. A maximum gain of -5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansoft HFSS simulation. Compared with the current state-of-the-art devices, the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.
A low-power high-performance configurable auto-gain control loop for a digital hearing aid SoC
Chengying Chen, Hainan Liu, Yong Hei, Jun Fan, Xiaoyu Hu
J. Semicond.  2013, 34(10): 105011  doi: 10.1088/1674-4926/34/10/105011

A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip (SoC) is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range (DR) improvement technique is also used to ensure the DR of the circuit in a low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a 1 V power supply, 1.6 kHz input frequency and 200 mVp-p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μ W, meeting the application requirements of hearing aid SoCs.

A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip (SoC) is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range (DR) improvement technique is also used to ensure the DR of the circuit in a low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a 1 V power supply, 1.6 kHz input frequency and 200 mVp-p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μ W, meeting the application requirements of hearing aid SoCs.
A new high-voltage level-shifting circuit for half-bridge power Ics
Moufu Kong, Xingbi Chen
J. Semicond.  2013, 34(10): 105012  doi: 10.1088/1674-4926/34/10/105012

In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well.

In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well.
SEMICONDUCTOR TECHNOLOGY
Low temperature Sn-rich Au-Sn wafer-level bonding
Zhiqiang Fang, Xu Mao, Jinling Yang, Fuhua Yang
J. Semicond.  2013, 34(10): 106001  doi: 10.1088/1674-4926/34/10/106001

Sn-rich Au-Sn solder bonding has been systematically investigated for low cost and low temperature wafer-level packaging of high-end MEMS devices. The AuSn2 phase with the highest Vickers-hardness among the four stable intermetallic compounds of the Au-Sn system makes a major contribution to the high bonding shear strength. The maximum shear strength of 64 MPa and a leak rate lower than 4.9×10-7 atm·cc/s have been obtained for Au46Sn54 solder bonded at 310℃. This wafer-level low cost bonding technique with high bonding strength can be applied to MEMS devices requiring low temperature packaging.

Sn-rich Au-Sn solder bonding has been systematically investigated for low cost and low temperature wafer-level packaging of high-end MEMS devices. The AuSn2 phase with the highest Vickers-hardness among the four stable intermetallic compounds of the Au-Sn system makes a major contribution to the high bonding shear strength. The maximum shear strength of 64 MPa and a leak rate lower than 4.9×10-7 atm·cc/s have been obtained for Au46Sn54 solder bonded at 310℃. This wafer-level low cost bonding technique with high bonding strength can be applied to MEMS devices requiring low temperature packaging.
A novel OPC method to reduce mask volume with yield-aware dissection
Chunlei Xie, Ye Chen, Zheng Shi
J. Semicond.  2013, 34(10): 106002  doi: 10.1088/1674-4926/34/10/106002

Growing data volume of masks tremendously increases manufacture cost. The cost increase is partially due to the complicated optical proximity corrections applied on mask design. In this paper, a yield-aware dissection method is presented. Based on the recognition of yield related mask context, the dissection result provides sufficient degrees of freedom to keep fidelity on critical sites while still retaining the frugality of modified designs. Experiments show that the final mask volume using the new method is reduced to about 50% of the conventional method.

Growing data volume of masks tremendously increases manufacture cost. The cost increase is partially due to the complicated optical proximity corrections applied on mask design. In this paper, a yield-aware dissection method is presented. Based on the recognition of yield related mask context, the dissection result provides sufficient degrees of freedom to keep fidelity on critical sites while still retaining the frugality of modified designs. Experiments show that the final mask volume using the new method is reduced to about 50% of the conventional method.