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Volume 37, Issue 8, Aug 2016
INVITED REVIEW PAPERS
Research progress of Si-based germanium materials and devices
Buwen Cheng, Cheng Li, Zhi Liu, Chunlai Xue
J. Semicond.  2016, 37(8): 081001  doi: 10.1088/1674-4926/37/8/081001

Si-based germanium is considered to be a promising platform for the integration of electronic and photonic devices due to its high carrier mobility, good optical properties, and compatibility with Si CMOS technology. However, some great challenges have to be confronted, such as: (1) the nature of indirect band gap of Ge; (2) the epitaxy of dislocation-free Ge layers on Si substrate; and (3) the immature technology for Ge devices. The aim of this paper is to give a review of the recent progress made in the field of epitaxy and optical properties of Ge heterostructures on Si substrate, as well as some key technologies on Ge devices. High crystal quality Ge epilayers, as well as Ge/SiGe multiple quantum wells with high Ge content, were successfully grown on Si substrate with a low-temperature Ge buffer layer. A local Ge condensation technique was proposed to prepare germanium-on-insulator (GOI) materials with high tensile strain for enhanced Ge direct band photoluminescence. The advances in formation of Ge n+p shallow junctions and the modulation of Schottky barrier height of metal/Ge contacts were a significant progress in Ge technology. Finally, the progress of Si-based Ge light emitters, photodetectors, and MOSFETs was briefly introduced. These results show that Si-based Ge heterostructure materials are promising for use in the next-generation of integrated circuits and optoelectronic circuits.

Si-based germanium is considered to be a promising platform for the integration of electronic and photonic devices due to its high carrier mobility, good optical properties, and compatibility with Si CMOS technology. However, some great challenges have to be confronted, such as: (1) the nature of indirect band gap of Ge; (2) the epitaxy of dislocation-free Ge layers on Si substrate; and (3) the immature technology for Ge devices. The aim of this paper is to give a review of the recent progress made in the field of epitaxy and optical properties of Ge heterostructures on Si substrate, as well as some key technologies on Ge devices. High crystal quality Ge epilayers, as well as Ge/SiGe multiple quantum wells with high Ge content, were successfully grown on Si substrate with a low-temperature Ge buffer layer. A local Ge condensation technique was proposed to prepare germanium-on-insulator (GOI) materials with high tensile strain for enhanced Ge direct band photoluminescence. The advances in formation of Ge n+p shallow junctions and the modulation of Schottky barrier height of metal/Ge contacts were a significant progress in Ge technology. Finally, the progress of Si-based Ge light emitters, photodetectors, and MOSFETs was briefly introduced. These results show that Si-based Ge heterostructure materials are promising for use in the next-generation of integrated circuits and optoelectronic circuits.
SEMICONDUCTOR PHYSICS
The algorithm for the piezoresistance coefficients of p-type polysilicon
Jian Wang, Rongyan Chuai
J. Semicond.  2016, 37(8): 082001  doi: 10.1088/1674-4926/37/8/082001

In order to improve the piezoresistance theory of polysilicon, based on the tunneling piezoresistance model, using the mechanisms of approximate valence band equation and shifts of the hole transfer and hole conduction mass by stress, a novel algorithm for the piezoresistance coefficients of p-type polysilicon is presented. It proposes three fundamental piezoresistance coefficients π11, π12 and π44 of the grain neutral and grain boundary regions, separately. With those piezoresistance coefficients, the gauge factors of the p-type polysilicon nanofilm and the p-type common polysilicon film are calculated, and then the plots of the gauge factor as a function of doping concentration are given, which are consistent with the experimental results.

In order to improve the piezoresistance theory of polysilicon, based on the tunneling piezoresistance model, using the mechanisms of approximate valence band equation and shifts of the hole transfer and hole conduction mass by stress, a novel algorithm for the piezoresistance coefficients of p-type polysilicon is presented. It proposes three fundamental piezoresistance coefficients π11, π12 and π44 of the grain neutral and grain boundary regions, separately. With those piezoresistance coefficients, the gauge factors of the p-type polysilicon nanofilm and the p-type common polysilicon film are calculated, and then the plots of the gauge factor as a function of doping concentration are given, which are consistent with the experimental results.
SEMICONDUCTOR MATERIALS
Fabrication of extremely thermal-stable GaN template on Mo substrate using double bonding and step annealing process
Qing Wang, Yang Liu, Yongjian Sun, Yuzhen Tong, Guoyi Zhang
J. Semicond.  2016, 37(8): 083001  doi: 10.1088/1674-4926/37/8/083001

A new layer transfer technique which comprised double bonding and a step annealing process was utilized to transfer the GaN epilayer from a sapphire substrate to a Mo substrate. Combined with the application of the thermal-stable bonding medium, the resulting two-inch-diameter GaN template showed extremely good stability under high temperature and low stress state. Moreover, no cracks and winkles were observed. The transferred GaN template was suitable for homogeneous epitaxial, thus could be used for the direct fabrication of vertical LED chips as well as power electron devices. It has been confirmed that the double bonding and step annealing technique together with the thermal-stable bonding layer could significantly improve the bonding strength and stress relief, finally enhancing the thermal stability of the transferred GaN template.

A new layer transfer technique which comprised double bonding and a step annealing process was utilized to transfer the GaN epilayer from a sapphire substrate to a Mo substrate. Combined with the application of the thermal-stable bonding medium, the resulting two-inch-diameter GaN template showed extremely good stability under high temperature and low stress state. Moreover, no cracks and winkles were observed. The transferred GaN template was suitable for homogeneous epitaxial, thus could be used for the direct fabrication of vertical LED chips as well as power electron devices. It has been confirmed that the double bonding and step annealing technique together with the thermal-stable bonding layer could significantly improve the bonding strength and stress relief, finally enhancing the thermal stability of the transferred GaN template.
Preparation and photocatalytic activities of 3D flower-like CuO nanostructures
Qingfei Fan, Qi Lan, Meili Zhang, Ximei Fan, Zuowan Zhou, Chaoliang Zhang
J. Semicond.  2016, 37(8): 083002  doi: 10.1088/1674-4926/37/8/083002

Hierarchical 3D flower-like CuO nanostructures on the Cu substrates were synthesized by a wet chemical method and subsequent heat treatment. The synthesis, structure and morphologies of obtained samples under different concentrations of Na2S2O3 were investigated in detail and the possible growth mechanisms of the 3D flower-like CuO nanostructures were discussed. Na2S2O3 plays a key role in the generation of the 3D flower-like CuO nanostructures. When the concentration of Na2S2O3 is more than 0.4 mol/L, the 3D flower-like CuO nanostructures can be prepared on the Cu foils. The photocatalytic performances were studied by analyzing the degradation of methyl orange (MO) in aqueous solution in the presence of hydroxide water (H2O2). The 3D flower-like CuO nanostructures exhibit higher photocatalytic activity (96.2% degradation rate) than commercial CuO particles (36.3% degradation rate). The origin of the higher photocatalytic activity of the 3D flower-like CuO nanostructures was also discussed.

Hierarchical 3D flower-like CuO nanostructures on the Cu substrates were synthesized by a wet chemical method and subsequent heat treatment. The synthesis, structure and morphologies of obtained samples under different concentrations of Na2S2O3 were investigated in detail and the possible growth mechanisms of the 3D flower-like CuO nanostructures were discussed. Na2S2O3 plays a key role in the generation of the 3D flower-like CuO nanostructures. When the concentration of Na2S2O3 is more than 0.4 mol/L, the 3D flower-like CuO nanostructures can be prepared on the Cu foils. The photocatalytic performances were studied by analyzing the degradation of methyl orange (MO) in aqueous solution in the presence of hydroxide water (H2O2). The 3D flower-like CuO nanostructures exhibit higher photocatalytic activity (96.2% degradation rate) than commercial CuO particles (36.3% degradation rate). The origin of the higher photocatalytic activity of the 3D flower-like CuO nanostructures was also discussed.
High haze textured surface B-doped ZnO-TCO films on wet-chemically etched glass substrates for thin film solar cells
Xinliang Chen, Jieming Liu, Jia Fang, Ze Chen, Ying Zhao, Xiaodan Zhang
J. Semicond.  2016, 37(8): 083003  doi: 10.1088/1674-4926/37/8/083003

Textured glass substrates with crater-like feature sizes of 5-30μm were obtained using the chemical etching method through adjusting the treatment round (R). Pyramid-like boron-doped zinc oxide (ZnO:B) films with feature sizes of 300-800 nm were deposited on the etched glass substrates by the metal organic chemical deposition (MOCVD) technique using water, diethylzinc and 1%-hydrogen-diluted diborane. The ZnO:B films on the etched glass with micro/nano double textures presented a much stronger light-scattering capability than the conventional ZnO:B on the flat glass and their electrical properties changed little. Typical etched glass-3R/ZnO:B exhibited a high root mean square (RMS) roughness of 160 nm. The haze values at the wavelengths of 550 nm and 850 nm for etched glass-3R/ZnO:B sample were 61% and 42%, respectively. Finally, the optimized etched glass/ZnO:B was applied in the silicon (Si) based thin film solar cells. The high haze etched glass/ZnO:B substrates have potential merits for thin film solar cells.

Textured glass substrates with crater-like feature sizes of 5-30μm were obtained using the chemical etching method through adjusting the treatment round (R). Pyramid-like boron-doped zinc oxide (ZnO:B) films with feature sizes of 300-800 nm were deposited on the etched glass substrates by the metal organic chemical deposition (MOCVD) technique using water, diethylzinc and 1%-hydrogen-diluted diborane. The ZnO:B films on the etched glass with micro/nano double textures presented a much stronger light-scattering capability than the conventional ZnO:B on the flat glass and their electrical properties changed little. Typical etched glass-3R/ZnO:B exhibited a high root mean square (RMS) roughness of 160 nm. The haze values at the wavelengths of 550 nm and 850 nm for etched glass-3R/ZnO:B sample were 61% and 42%, respectively. Finally, the optimized etched glass/ZnO:B was applied in the silicon (Si) based thin film solar cells. The high haze etched glass/ZnO:B substrates have potential merits for thin film solar cells.
Solvothermal synthesis of Bi2O3/BiVO4 heterojunction with enhanced visible-light photocatalytic performances
Ying Wu, Jing Wang, Yunfang Huang, Yuelin Wei, Zhixian Sun, Xuanqing Zheng, Chengkun Zhang, Ningling Zhou, Leqing Fan, Jihuai Wu
J. Semicond.  2016, 37(8): 083004  doi: 10.1088/1674-4926/37/8/083004

Novel, three-dimensional, flower-like Bi2O3/BiVO4 heterojunction photocatalysts have been prepared by the combination of homogeneous precipitation and two-step solvothermal method followed by thermal solution of NaOH etching process. The as-obtained samples were fully characterized by X-ray diffraction, scanning electron microscopy, energy dispersive X-ray analysis, Brunauer-Emmett-Teller surface area, and UV-vis diffuse-reflectance spectroscopy in detail. The crystallinity, microstructure, specific surface area, optical property and photocatalytic activity of samples greatly changed depending on solvothermal reaction time. The photocatalytic activities of samples were evaluated on the degradation of methyl orange (MO) under visible-light irradiation. The Bi2O3/BiVO4 exhibited much higher photocatalytic activities than pure BiVO4 and conventional TiO2 (P25). The result revealed that the three-dimensional heterojunction played a critical role in the separation of the electron and hole pairs and enhancement of the interfacial charge transfer efficiency, which was responsible for the enhanced photocatalytic activity.

Novel, three-dimensional, flower-like Bi2O3/BiVO4 heterojunction photocatalysts have been prepared by the combination of homogeneous precipitation and two-step solvothermal method followed by thermal solution of NaOH etching process. The as-obtained samples were fully characterized by X-ray diffraction, scanning electron microscopy, energy dispersive X-ray analysis, Brunauer-Emmett-Teller surface area, and UV-vis diffuse-reflectance spectroscopy in detail. The crystallinity, microstructure, specific surface area, optical property and photocatalytic activity of samples greatly changed depending on solvothermal reaction time. The photocatalytic activities of samples were evaluated on the degradation of methyl orange (MO) under visible-light irradiation. The Bi2O3/BiVO4 exhibited much higher photocatalytic activities than pure BiVO4 and conventional TiO2 (P25). The result revealed that the three-dimensional heterojunction played a critical role in the separation of the electron and hole pairs and enhancement of the interfacial charge transfer efficiency, which was responsible for the enhanced photocatalytic activity.
SEMICONDUCTOR DEVICES
Development of 17 kV 4H-SiC PiN diode
Runhua Huang, Yonghong Tao, Ling Wang, Gang Chen, Song Bai, Rui Li, Zhifei Zhao
J. Semicond.  2016, 37(8): 084001  doi: 10.1088/1674-4926/37/8/084001

The design, fabrication, and electrical characteristics of a 4H-SiC PiN diode with breakdown voltage higher than 17 kV are presented. The three-zone JTE has been used in the fabrication. Numerical simulations have been performed to optimize the parameters of the edge termination technique. The epilayer properties of the N-type are 175μm with a doping of 2×1014cm-3. With the three-zone JTE, a typical breakdown voltage of 17 kV has been achieved.

The design, fabrication, and electrical characteristics of a 4H-SiC PiN diode with breakdown voltage higher than 17 kV are presented. The three-zone JTE has been used in the fabrication. Numerical simulations have been performed to optimize the parameters of the edge termination technique. The epilayer properties of the N-type are 175μm with a doping of 2×1014cm-3. With the three-zone JTE, a typical breakdown voltage of 17 kV has been achieved.
Design, fabrication and characterising of 100 W GaN HEMT for Ku-bandapplication
Chunjiang Ren, Shichang Zhong, Yuchao Li, Zhonghui Li, Yuechan Kong, Tangsheng Chen
J. Semicond.  2016, 37(8): 084002  doi: 10.1088/1674-4926/37/8/084002

Ku-band GaN power transistor with output power over 100 W under the pulsed operation mode is presented. A high temperature AlN nucleation together with an Fe doped GaN buffer was introduced for the developed GaN HEMT. The AlGaN/GaN hetero-structure deposited on 3 inch SiC substrate exhibited a 2DEG hall mobility and density of~2100 cm2/(V·s) and 1.0×1013 cm-2, respectively, at room temperature. Dual field plates were introduced to the designed 0.25 μm GaN HEMT and the source connected field plate was optimized for minimizing the peak field plate near the drain side of the gate, while maintaining excellent power gain performance for Ku-band application. The load-pull measurement at 14 GHz showed a power density of 5.2 W/mm for the fabricated 400 μm gate periphery GaN HEMT operated at a drain bias of 28 V. A Ku-band internally matched GaN power transistor was developed with two 10.8 mm gate periphery GaN HEMT chips combined. The GaN power transistor exhibited an output power of 102 W at 13.3 GHz and 32 V operating voltage under pulsed operation mode with a pulse width of 100 μs and duty cycle of 10%. The associated power gain and power added efficiency were 9.2 dB and 48%, respectively. To the best of the authors' knowledge, the PAE is the highest for Ku-band GaN power transistor with over 100 W output power.

Ku-band GaN power transistor with output power over 100 W under the pulsed operation mode is presented. A high temperature AlN nucleation together with an Fe doped GaN buffer was introduced for the developed GaN HEMT. The AlGaN/GaN hetero-structure deposited on 3 inch SiC substrate exhibited a 2DEG hall mobility and density of~2100 cm2/(V·s) and 1.0×1013 cm-2, respectively, at room temperature. Dual field plates were introduced to the designed 0.25 μm GaN HEMT and the source connected field plate was optimized for minimizing the peak field plate near the drain side of the gate, while maintaining excellent power gain performance for Ku-band application. The load-pull measurement at 14 GHz showed a power density of 5.2 W/mm for the fabricated 400 μm gate periphery GaN HEMT operated at a drain bias of 28 V. A Ku-band internally matched GaN power transistor was developed with two 10.8 mm gate periphery GaN HEMT chips combined. The GaN power transistor exhibited an output power of 102 W at 13.3 GHz and 32 V operating voltage under pulsed operation mode with a pulse width of 100 μs and duty cycle of 10%. The associated power gain and power added efficiency were 9.2 dB and 48%, respectively. To the best of the authors' knowledge, the PAE is the highest for Ku-band GaN power transistor with over 100 W output power.
A novel high performance SemiSJ-CSTBT with p-pillar under the bottom of the trench gate
Yan Jia, Hong Chen, Ji Tan, Shuojin Lu, Yangjun Zhu
J. Semicond.  2016, 37(8): 084003  doi: 10.1088/1674-4926/37/8/084003

A novel high performance SemiSJ-CSTBT is proposed with the p-pillar under the bottom of the trench gate. The inserted p-pillar with the neighbouring n-drift region forms a lateral P/N junction, which can adjust the electric distribution in the forward-blocking mode to achieve a higher breakdown voltage compared to the conventional CSTBT. Also, the p-pillar can act as a hole collector at turn-off, which significantly enhances the turn-off speed and obtains a lower turn-off switching loss. Although the turn-off switching loss decreases as the depth of the p-pillar increases, there is no need for a very deep p-pillar. The associated voltage overshoot at turn-off increases dramatically with increasing the depth of p-pillar, which may cause destruction of the devices. Plus, this will add difficulty and cost to the manufacturing process of this new structure. Therefore, the proposed SemiSJ-CSTBT offers considerably better robustness compared to the conventional CSTBT and SJ-CSTBT. The simulation results show that the SemiSJ-CSTBT exhibits an increase in breakdown voltage by 160 V (13%) and a reduction of turn-off switching loss by approximately 15%.

A novel high performance SemiSJ-CSTBT is proposed with the p-pillar under the bottom of the trench gate. The inserted p-pillar with the neighbouring n-drift region forms a lateral P/N junction, which can adjust the electric distribution in the forward-blocking mode to achieve a higher breakdown voltage compared to the conventional CSTBT. Also, the p-pillar can act as a hole collector at turn-off, which significantly enhances the turn-off speed and obtains a lower turn-off switching loss. Although the turn-off switching loss decreases as the depth of the p-pillar increases, there is no need for a very deep p-pillar. The associated voltage overshoot at turn-off increases dramatically with increasing the depth of p-pillar, which may cause destruction of the devices. Plus, this will add difficulty and cost to the manufacturing process of this new structure. Therefore, the proposed SemiSJ-CSTBT offers considerably better robustness compared to the conventional CSTBT and SJ-CSTBT. The simulation results show that the SemiSJ-CSTBT exhibits an increase in breakdown voltage by 160 V (13%) and a reduction of turn-off switching loss by approximately 15%.
Application of the thermoelectric MEMS microwave power sensor in a powerradiation monitoring system
Bo Gao, Jing Yang, Si Jiang, Debo Wang
J. Semicond.  2016, 37(8): 084004  doi: 10.1088/1674-4926/37/8/084004

A power radiation monitoring system based on thermoelectric MEMS microwave power sensors is studied. This monitoring system consists of three modules: a data acquisition module, a data processing and display module, and a data sharing module. It can detect the power radiation in the environment and the date information can be processed and shared. The measured results show that the thermoelectric MEMS microwave power sensor and the power radiation monitoring system both have a relatively good linearity. The sensitivity of the thermoelectric MEMS microwave power sensor is about 0.101 mV/mW, and the sensitivity of the monitoring system is about 0.038 V/mW. The voltage gain of the monitoring system is about 380 times, which is relatively consistent with the theoretical value. In addition, the low-frequency and low-power module in the monitoring system is adopted in order to reduce the electromagnetic pollution and the power consumption, and this work will extend the application of the thermoelectric MEMS microwave power sensor in more areas.

A power radiation monitoring system based on thermoelectric MEMS microwave power sensors is studied. This monitoring system consists of three modules: a data acquisition module, a data processing and display module, and a data sharing module. It can detect the power radiation in the environment and the date information can be processed and shared. The measured results show that the thermoelectric MEMS microwave power sensor and the power radiation monitoring system both have a relatively good linearity. The sensitivity of the thermoelectric MEMS microwave power sensor is about 0.101 mV/mW, and the sensitivity of the monitoring system is about 0.038 V/mW. The voltage gain of the monitoring system is about 380 times, which is relatively consistent with the theoretical value. In addition, the low-frequency and low-power module in the monitoring system is adopted in order to reduce the electromagnetic pollution and the power consumption, and this work will extend the application of the thermoelectric MEMS microwave power sensor in more areas.
Investigation and solution of low yield problem for phase change memory with lateral fully-confined structure
Yaling Zhou, Xiaofeng Wang, Yingchun Fu, Xiaodong Wang, Fuhua Yang
J. Semicond.  2016, 37(8): 084005  doi: 10.1088/1674-4926/37/8/084005

This paper mainly focuses on solving the low yield problem for lateral phase change random access memory with a fully confined phase change material node. Improper over-etching and bad step-coverage of physical vapor deposition were the main reasons for the poor contact quality, which leads to the low yield problem. Process improvement was carried out to better control over-etching within 10 nm. Atomic layer deposition process was used to replace physical vapor deposition to guarantee good step coverage. Contrasting cross-sectional photos taken by scanning electron microscopy showed great improvement in contact quality. The atom layer deposition process was demonstrated to have good prospects in nano-contact for phase change memory application.

This paper mainly focuses on solving the low yield problem for lateral phase change random access memory with a fully confined phase change material node. Improper over-etching and bad step-coverage of physical vapor deposition were the main reasons for the poor contact quality, which leads to the low yield problem. Process improvement was carried out to better control over-etching within 10 nm. Atomic layer deposition process was used to replace physical vapor deposition to guarantee good step coverage. Contrasting cross-sectional photos taken by scanning electron microscopy showed great improvement in contact quality. The atom layer deposition process was demonstrated to have good prospects in nano-contact for phase change memory application.
Ferroelectricity-modulated resistive switching in Pt/Si:HfO2/HfO2-x/Pt memory
Ran Jiang, Xianghao Du, Zuyin Han
J. Semicond.  2016, 37(8): 084006  doi: 10.1088/1674-4926/37/8/084006

It is investigated for the effect of a ferroelectric Si:HfO2 thin film on the resistive switching in a stacked Pt/Si:HfO2/highly-oxygen-deficient HfO2-x/Pt structure. Improved resistance performance was observed. It was concluded that the observed resistive switching behavior was related to the modulation of the width and height of a depletion barrier in the HfO2-x layer, which was caused by the Si:HfO2 ferroelectric polarization field effect. Reliable switching reproducibility and long data retention were observed in these memory cells, suggesting their great potential in non-volatile memories applications with full compatibility and simplicity.

It is investigated for the effect of a ferroelectric Si:HfO2 thin film on the resistive switching in a stacked Pt/Si:HfO2/highly-oxygen-deficient HfO2-x/Pt structure. Improved resistance performance was observed. It was concluded that the observed resistive switching behavior was related to the modulation of the width and height of a depletion barrier in the HfO2-x layer, which was caused by the Si:HfO2 ferroelectric polarization field effect. Reliable switching reproducibility and long data retention were observed in these memory cells, suggesting their great potential in non-volatile memories applications with full compatibility and simplicity.
Influence of the thickness change of the wave-guide layers on the threshold current of GaAs-based laser diode
Yi Pang, Xiang Li, Baiqin Zhao
J. Semicond.  2016, 37(8): 084007  doi: 10.1088/1674-4926/37/8/084007

The paper mainly deals with theoretical investigations of the effect of the thickness change of the waveguide layers on the threshold current. It is analyzed according to the result of a numerical simulation that asks how does the shift of the active region position affect the threshold current for a single quantum well (SQW) and double quantum well (DQW) laser diode (LD) with a relatively narrow waveguide. It is found that the variation trend of threshold current and optimum position of QW are different in SQW and DQW LD with 0.2 μm-thick waveguide, which may be due to the higher variation rate of optical loss in DQW LD with the shift of the active region. It is also found that in terms of either SQW or DQW LD, the variation tendency of the threshold current with a different loss coefficient of the p-cladding layer makes little difference for the relatively narrow waveguide LD. Moreover, the variation trend of the threshold current and the optimum position of QW is almost the same in SQW and DQW LD with 0.8μm-thick waveguide, because the optical loss is small enough and the threshold current is dominated by the optical confinement factor (OCF) in QW.

The paper mainly deals with theoretical investigations of the effect of the thickness change of the waveguide layers on the threshold current. It is analyzed according to the result of a numerical simulation that asks how does the shift of the active region position affect the threshold current for a single quantum well (SQW) and double quantum well (DQW) laser diode (LD) with a relatively narrow waveguide. It is found that the variation trend of threshold current and optimum position of QW are different in SQW and DQW LD with 0.2 μm-thick waveguide, which may be due to the higher variation rate of optical loss in DQW LD with the shift of the active region. It is also found that in terms of either SQW or DQW LD, the variation tendency of the threshold current with a different loss coefficient of the p-cladding layer makes little difference for the relatively narrow waveguide LD. Moreover, the variation trend of the threshold current and the optimum position of QW is almost the same in SQW and DQW LD with 0.8μm-thick waveguide, because the optical loss is small enough and the threshold current is dominated by the optical confinement factor (OCF) in QW.
SEMICONDUCTOR INTEGRATED CIRCUITS
A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS
Xiangning Fan, Jian Tao, Kuan Bao, Zhigong Wang
J. Semicond.  2016, 37(8): 085001  doi: 10.1088/1674-4926/37/8/085001

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximumⅡP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch (I or Q) ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm2 including pads.

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximumⅡP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch (I or Q) ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm2 including pads.
50 MHz dual-mode buck DC-DC converter
Zhang Zhang, Xing Wang, Wencheng Yu, Ye Tan, Yizhong Yang, Guangjun Xie
J. Semicond.  2016, 37(8): 085002  doi: 10.1088/1674-4926/37/8/085002

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS (BIAS current). A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS (BIAS current). A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.
Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods
Zhan Gao, Dan Ren, Shuai Yan, Xiaoyu Xu, Zhuoxiang Ren
J. Semicond.  2016, 37(8): 085003  doi: 10.1088/1674-4926/37/8/085003

Sensitivity analysis methods help to deal with the challenges of process variation in extraction of parasitic capacitances in an integrated circuit. The dual discrete geometric methods (DGMs), which have been recently utilized to extract parasitic capacitances, are reviewed. The computation method based on the dual DGMs for sensitivities of capacitances with respect to the given process parameters is presented. As the dual DGMs utilize scalar electric potential is unknown, the capacitances are obtained effectively, and then the sensitivities are calculated conveniently.

Sensitivity analysis methods help to deal with the challenges of process variation in extraction of parasitic capacitances in an integrated circuit. The dual discrete geometric methods (DGMs), which have been recently utilized to extract parasitic capacitances, are reviewed. The computation method based on the dual DGMs for sensitivities of capacitances with respect to the given process parameters is presented. As the dual DGMs utilize scalar electric potential is unknown, the capacitances are obtained effectively, and then the sensitivities are calculated conveniently.
SEMICONDUCTOR TECHNOLOGY
Synergetic effect of chelating agent and nonionic surfactant for benzotriazoleremoval on post Cu-CMP cleaning
Yanlei Li, Yuling Liu, Chenwei Wang, Yue Li
J. Semicond.  2016, 37(8): 086001  doi: 10.1088/1674-4926/37/8/086001

The cleaning of copper interconnects after chemical mechanical planarization (CMP) process is a critical step in integrated circuits (ICs) fabrication. Benzotriazole (BTA), which is used as corrosion inhibitor in the copper CMP slurry, is the primary source for the formation of organic contaminants. The presence of BTA can degrade the electrical properties and reliability of ICs which needs to be removed by using an effective cleaning solution. In this paper, an alkaline cleaning solution was proposed. The alkaline cleaning solution studied in this work consists of a chelating agent and a nonionic surfactant. The removal of BTA was characterized by contact angle measurements and potentiodynamic polarization studies. The cleaning properties of the proposed cleaning solution on a 300 mm copper patterned wafer were also quantified, total defect counts after cleaning was studied, scanning electron microscopy (SEM) review was used to identify types of BTA to confirm the ability of cleaning solution for BTA removal. All the results reveal that the chelating agent can effectively remove the BTA residual, nonionic surfactant can further improve the performance.

The cleaning of copper interconnects after chemical mechanical planarization (CMP) process is a critical step in integrated circuits (ICs) fabrication. Benzotriazole (BTA), which is used as corrosion inhibitor in the copper CMP slurry, is the primary source for the formation of organic contaminants. The presence of BTA can degrade the electrical properties and reliability of ICs which needs to be removed by using an effective cleaning solution. In this paper, an alkaline cleaning solution was proposed. The alkaline cleaning solution studied in this work consists of a chelating agent and a nonionic surfactant. The removal of BTA was characterized by contact angle measurements and potentiodynamic polarization studies. The cleaning properties of the proposed cleaning solution on a 300 mm copper patterned wafer were also quantified, total defect counts after cleaning was studied, scanning electron microscopy (SEM) review was used to identify types of BTA to confirm the ability of cleaning solution for BTA removal. All the results reveal that the chelating agent can effectively remove the BTA residual, nonionic surfactant can further improve the performance.