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Volume 37, Issue 9, Sep 2016


  • Photodetectors based on two dimensional materials

    Zheng Lou, Zhongzhu Liang, Guozhen Shen

    J. Semicond.  2016, 37(9): 091001

    doi: 10.1088/1674-4926/37/9/091001

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    Two-dimensional (2D) materials with unique properties have received a great deal of attention in recent years. This family of materials has rapidly established themselves as intriguing building blocks for versatile nanoelectronic devices that offer promising potential for use in next generation optoelectronics, such as photodetectors. Furthermore, their optoelectronic performance can be adjusted by varying the number of layers. They have demonstrated excellent light absorption, enabling ultrafast and ultrasensitive detection of light in photodetectors, especially in their single-layer structure. Moreover, due to their atomic thickness, outstanding mechanical flexibility, and large breaking strength, these materials have been of great interest for use in flexible devices and strain engineering. Toward that end, several kinds of photodetectors based on 2D materials have been reported. Here, we present a review of the state-of-the-art in photodetectors based on graphene and other 2D materials, such as the graphene, transition metal dichalcogenides, and so on.


  • Scaling relation of domain competition on (2+1)-dimensional ballistic deposition model with surface diffusion

    Kenyu Osada, Hiroyasu Katsuno, Toshiharu Irisawa, Yukio Saito

    J. Semicond.  2016, 37(9): 092001

    doi: 10.1088/1674-4926/37/9/092001

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    During heteroepitaxial overlayer growth multiple crystal domains nucleated on a substrate surface compete with each other in such a manner that a domain covered by neighboring ones stops growing. The number density of active domains ρ decreases as the height h increases. A simple scaling argument leads to a scaling law of ρ~h-γ with a coarsening exponent γ=d/z, where d is the dimension of the substrate surface and z the dynamic exponent of a growth front. This scaling relation is confirmed by performing kinetic Monte Carlo simulations of the ballistic deposition model on a two-dimensional (d=2) surface, even when an isolated deposited particle diffuses on a crystal surface.

  • Thermoelectric properties of Al-doped ZnO: experiment and simulation

    S. Jantrasee, P. Moontragoon, S. Pinitsoontorn

    J. Semicond.  2016, 37(9): 092002

    doi: 10.1088/1674-4926/37/9/092002

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    Advancement in doping other elements, such as Ce, Dy, Ni, Sb, In and Ga in ZnO[1], have stimulated great interest for high-temperature thermoelectric application. In this work, the effects of Al-doping in a ZnO system on the electronic structure and thermoelectric properties are presented, by experiment and calculation.Nanosized powders of Zn1-xAlxO (x=0, 0.01, 0.02, 0.03 and 0.06) were synthesized by hydrothermal method. From XRD results, all samples contain ZnO as the main phase and ZnAl2O4 (spinel phase) peaks were visible when Al additive concentrations were just 6 at%. The shape of the samples changed and the particle size decreased with increasing Al concentration. Seebeck coefficients, on the other hand, did not vary significantly. They were negative and the absolute values increased with temperature. However, the electrical resistivity decreased significantly for higher Al content.The electronic structure calculations were carried out using the open-source software package ABINIT[2], which is based on DFT. The energy band gap, density of states of Al-doped ZnO were investigated using PAW pseudopotential method within the LDA+U. The calculated density of states was then used in combination with the Boltzmann transport equation[3] to calculate the thermoelectric parameters of Al-doped ZnO. The electronic band structures showed that the position of the Fermi level of the doped sample was shifted upwards in comparison to the undoped one. After doping Al in ZnO, the energy band gap was decreased, Seebeck coefficient and electrical conductivity were increased.Finally, the calculated results were compared with the experimental results. The good agreement of thermoelectric properties between the calculation and the experimental results were obtained.

  • Semiconductor steady state defect effective Fermi level and deep level transient spectroscopy depth profiling

    Ken K. Chin, Zimeng Cheng

    J. Semicond.  2016, 37(9): 092003

    doi: 10.1088/1674-4926/37/9/092003

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    The widely used deep level transient spectroscopy (DLTS) theory and data analysis usually assume that the defect level distribution is uniform through the depth of the depletion region of the n-p junction. In this work we introduce the concept of effective Fermi level of the steady state of semiconductor, by using which deep level transient spectroscopy depth profiling (DLTSDP) is proposed. Based on the relationship of its transition free energy level (TFEL) and the effective Fermi level, the rules of detectivity of the defect levels are listed. Computer simulation of DLTSDP is presented and compared with experimental data. The experimental DLTS data are compared with what the DLTSDP selection rules predicted. The agreement is satisfactory.

  • Magnetopolaron effects on the optical absorptions in a parabolic quantum dot

    Shihua Chen

    J. Semicond.  2016, 37(9): 092004

    doi: 10.1088/1674-4926/37/9/092004

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    We investigate the influence of magnetic field on the linear and nonlinear optical absorptions in a parabolic quantum dot (QD) through electron-LO-phonon interaction by using the Lee-Low-Pines-Huybrecht variational calculation for all coupling strengths. We apply our calculations to GaAs which is a good candidate in Ⅲ-V group semiconductors. We find that all the absorption spectra are strongly affected by the electron-LO-phonon interaction, the applied magnetic field, and the Coulomb binding potential. Furthermore, due to the Zeeman splitting, the response of all the absorption values in transition (+1→0) and (-1→0) closely depends on the magnetic field increasing.


  • Steady-state solution growth of microcrystalline silicon on nanocrystalline seed layers on glass

    R. Bansen, C. Ehlers, Th. Teubner, T. Boeck

    J. Semicond.  2016, 37(9): 093001

    doi: 10.1088/1674-4926/37/9/093001

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    The growth of polycrystalline silicon layers on glass from tin solutions at low temperatures is presented. This approach is based on the steady-state solution growth of Si crystallites on nanocrystalline seed layers, which are prepared in a preceding process step. Scanning electron microscopy and atomic force microscopy investigations reveal details about the seed layer surfaces, which consist of small hillocks, as well as about Sn inclusions and gaps along the glass substrate after solution growth. The successful growth of continuous microcrystalline Si layers with grain sizes up to several ten micrometers shows the feasibility of the process and makes it interesting for photovoltaics.

  • Optoelectronic properties and Seebeck coefficient in SnSe thin films

    K S Urmila, T A Namitha, J Rajani, R R Philip, B Pradeep

    J. Semicond.  2016, 37(9): 093002

    doi: 10.1088/1674-4926/37/9/093002

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    SnSe thin films of thickness 180 nm have been deposited on glass substrates by reactive evaporation at an optimized substrate temperature of 523±5 K and pressure of 10-5 mbar. The as-prepared SnSe thin films are characterized for their structural, optical and electrical properties by various experimental techniques. The p-type conductivity, near-optimum direct band gap, high absorption coefficient and good photosensitivity of the SnSe thin film indicate its suitability for photovoltaic applications. The optical constants, loss factor, quality factor and optical conductivity of the films are evaluated. The results of Hall and thermoelectric power measurements are correlated to determine the density of states, Fermi energy and effective mass of carriers and are obtained as 2.8×1017cm-3, 0.03 eV and 0.05 m0 respectively. The high Seebeck coefficient≈7863 μV/K, reasonably good power factor≈7.2×10-4 W/(m·K2) and thermoelectric figure of merit≈1.2 observed at 42 K suggests that, on further work, the prepared SnSe thin films can also be considered as a possible candidate for cryogenic thermoelectric applications.

  • Bulk heterojunction thin film formation by single and dual feed ultrasonic spray method for application in organic solar cells

    D. M. Marathe, H. S. Tarkas, M. S. Mahajan, G. S. Lonkar, S. R. Tak, J. V. Sali

    J. Semicond.  2016, 37(9): 093003

    doi: 10.1088/1674-4926/37/9/093003

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    We here present a way of preparing the polymer:fullerene BHJ using dual feed method which can lead to formation of pure phases. In this report, we present results of our initial experiments in this direction. The effect of process parameters on the thickness and surface roughness of the active layer has been discussed. The structural and optical properties have been studied using the optical microscope, UV-visible spectroscopy and photoluminescence spectroscopy. Significant PL quenching indicates efficient charge separation in the BHJ formed using this technique. We have also compared the BHJ thin films prepared with this dual feed ultrasonic technique with the single feed spray method. The BHJ formed using this technique has been used as an active layer in OSC.

  • A thin transition film formed by plasma exposure contributes to the germanium surface hydrophilicity

    Shumei Lai, Danfeng Mao, Zhiwei Huang, Yihong Xu, Songyan Chen, Cheng Li, Wei Huang, Dingliang Tang

    J. Semicond.  2016, 37(9): 093004

    doi: 10.1088/1674-4926/37/9/093004

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    Plasma treatment and 10% NH4OH solution rinsing were performed on a germanium (Ge) surface. It was found that the Ge surface hydrophilicity after O2 and Ar plasma exposure was stronger than that of samples subjected to N2 plasma exposure. This is because the thin GeOx film formed on Ge by O2 or Ar plasma is more hydrophilic than GeOxNy formed by N2 plasma treatment. A flat (RMS<0.5 nm) Ge surface with high hydrophilicity (contact angle smaller than 3°) was achieved by O2 plasma treatment, showing its promising application in Ge low-temperature direct wafer bonding.


  • A transformed analytical model for thermal noise of FinFET based on fringing field approximation

    Savitesh Madhulika Sharma, S. Dasgupta, M. V. Kartikeyan

    J. Semicond.  2016, 37(9): 094001

    doi: 10.1088/1674-4926/37/9/094001

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    This paper delineates the effect of nonplanar structure of FinFETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended (underlap) S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional (3-D) structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 dB and 100 Ω respectively and optimum admittance increases to 5.45 mω at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.

  • Investigation of Coulomb scattering on sSi/Si0.5Ge0.5/sSOI quantum-well p-MOSFETs

    Jiao Wen, Qiang Liu, Chang Liu, Yize Wang, Bo Zhang, Zhongying Xue, Zengfeng Di, Wenjie Yu, Qingtai Zhao

    J. Semicond.  2016, 37(9): 094002

    doi: 10.1088/1674-4926/37/9/094002

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    sSi/Si0.5Ge0.5/sSOI quantum-well (QW) p-MOSFETs with HfO2/TiN gate stack were fabricated and characterized. According to the low temperature experimental results, carrier mobility of the strained Si0.5Ge0.5 QW p-MOSFET was mainly governed by phonon scattering from 300 to 150 K and Coulomb scattering below 150 K, respectively. Coulomb scattering was intensified by the accumulated inversion charges in the Si cap layer of this Si/SiGe heterostructure, which led to a degradation of carrier mobility in the SiGe channel, especially at low temperature.

  • Vertical-dual-source tunnel FETs with steeper subthreshold swing

    Zhi Jiang, Yiqi Zhuang, Cong Li, Ping Wang, Yuqi Liu

    J. Semicond.  2016, 37(9): 094003

    doi: 10.1088/1674-4926/37/9/094003

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    In order to improve the drive current and subthreshold swing (SS), a novel vertical-dual-source tunneling field-effect transistor (VDSTFET) device is proposed in this paper. The influence of source height, channel length and channel thickness on the device are investigated through two-dimensional numerical simulations. Si-VDSTFET have greater tunneling area and thinner channel, showing an on-current as high as 1.24 μA at gate voltage of 0.8 V and drain voltage of 0.5 V, off-current of less than 0.1 fA, an improved average subthreshold swing of 14 mV/dec, and a minimum point slope of 4 mV/dec.

  • A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

    Changjun Liao, Jizhi Liu, Zhiwei Liu

    J. Semicond.  2016, 37(9): 094004

    doi: 10.1088/1674-4926/37/9/094004

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    The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the It2 of the HBT trigger SCR is 80% more than that of the MLSCR.


  • A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

    Yiqi Mao, Tongqiang Gao, Xiaodong Xu, Haigang Yang, Xinxia Cai

    J. Semicond.  2016, 37(9): 095001

    doi: 10.1088/1674-4926/37/9/095001

    Abstract Full Text PDF Get Citation

    A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm2. It achieves a sensitivity of -80 dBm for 10-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.

  • A low-noise widely tunable Gm-C filter with frequency calibration

    Yu Wang, Jing Liu, Na Yan, Hao Min

    J. Semicond.  2016, 37(9): 095002

    doi: 10.1088/1674-4926/37/9/095002

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    A fourth-order Gm-C Chebyshev low-pass filter is presented as channel selection filter for reconfigurable multi-mode wireless receivers. Low-noise technologies are proposed in optimizing the noise characteristics of both the Gm cells and the filter topology. A frequency tuning strategy is used by tuning both the transconductance of the Gm cells and the capacitance of the capacitor banks. To achieve accurate cut-off frequencies, an on-chip calibration circuit is presented to compensate for the frequency inaccuracy introduced by process variation. The filter is fabricated in a 0.13 μm CMOS process. It exhibits a wide programmable bandwidth from 322.5 kHz to 20 MHz. Measured results show that the filter has low input referred noise of 5.9 nV/√Hz and high out-of-band ⅡP3 of 16.2 dBm. It consumes 4.2 and 9.5 mW from a 1 V power supply at its lowest and highest cut-off frequencies respectively.

  • A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission

    Zhang Zhang, Ye Tan, Jianmin Zeng, Xu Han, Xin Cheng, Guangjun Xie

    J. Semicond.  2016, 37(9): 095003

    doi: 10.1088/1674-4926/37/9/095003

    Abstract Full Text PDF Get Citation

    A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission is presented. Data and power are transmitted to the stimulator by mutual inductance coupling, while the in-vitro controller encodes the stimulation parameters. The stimulator integrates the digital control module and can generate the bipolar current with equal amplitude in four channels. In order to reduce power consumption, a novel controlled threshold voltage cancellation rectifier is proposed in this paper to provide the supply voltage of the stimulator. The monolithic stimulator was fabricated in a SMIC 0.18 μm 1-poly 6-metal mixed-signal CMOS process, occupying 0.23 mm2, and consumes 180 μW on average. Compared with previously published stimulators, this design has advantages of large stimulated current (0-0.8 mA) with the double low-voltage supply (1.8 and 3.3 V), and high-level integration.

  • Low-noise sub-harmonic injection locked multiloop ring oscillator

    Weilin Xu, Di Wu, Xueming Wei, Baolin Wei, Jihai Duan, Fadi Gui

    J. Semicond.  2016, 37(9): 095004

    doi: 10.1088/1674-4926/37/9/095004

    Abstract Full Text PDF Get Citation

    A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband (UWB) wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 μm 1P6M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of -112.37 dBc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 mA excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 dB phase noise improvement at 1 MHz offset compared to the standard topology.


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