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Volume 38, Issue 12, Dec 2017

    INVITED REVIEW PAPERS

  • High-speed photodetectors in optical communication system

    Zeping Zhao, Jianguo Liu, Yu Liu, Ninghua Zhu

    J. Semicond.  2017, 38(12): 121001

    doi: 10.1088/1674-4926/38/12/121001

    Abstract Full Text PDF Get Citation

    This paper presents a review and discussion for high-speed photodetectors and their applications on optical communications and microwave photonics. A detailed and comprehensive demonstration of high-speed photodetectors from development history, research hotspots to packaging technologies is provided to the best of our knowledge. A few typical applications based on photodetectors are also illustrated, such as free-space optical communications, radio over fiber and millimeter terahertz signal generation systems.

  • SEMICONDUCTOR PHYSICS

  • Direct evidence of traps controlling the carriers transport in SnO2 nanobelts

    Olivia M. Berengue, Adenilson J. Chiquito

    J. Semicond.  2017, 38(12): 122001

    doi: 10.1088/1674-4926/38/12/122001

    Abstract Full Text PDF Get Citation

    This work reports on direct evidence of localized states in undoped SnO2 nanobelts. Effects of disorder and electron localization were observed in Schottky barrier dependence on the temperature and in thermally stimulated currents. A transition from thermal activation to hopping transport mechanisms was also observed. The energy levels found by thermally stimulated current experiments were in close agreement with transport data confirming the role of localization in determining the properties of devices.

  • Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

    Neeraj Jain, Balwinder Raj

    J. Semicond.  2017, 38(12): 122002

    doi: 10.1088/1674-4926/38/12/122002

    Abstract Full Text PDF Get Citation

    Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (Ion), OFF current (Ioff) and Ion/Ioff ratio. The potential benefits of SOI FinFET at drain-to-source voltage, VDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (AV), output conductance (gd), trans-conductance (gm), gate capacitance (Cgg), and cut-off frequency (fT = gm/2πCgg) with spacer region variations.

  • Influence of oxygen doping on resistive-switching characteristic of a-Si/c-Si device

    Jiahua Zhang, Da Chen, Shihua Huang

    J. Semicond.  2017, 38(12): 122003

    doi: 10.1088/1674-4926/38/12/122003

    Abstract Full Text PDF Get Citation

    The influence of oxygen doping on resistive-switching characteristics of Ag/a-Si/p+-c-Si device was investigated. By oxygen doping in the growth process of amorphous silicon, the device resistive-switching performances, such as the ON/OFF resistance ratios, yield and stability were improved, which may be ascribed to the significant reduction of defect density because of oxygen incorporation. The device I–V characteristics are strongly dependent on the oxygen doping concentration. As the oxygen doping concentration increases, the Si-rich device gradually transforms to an oxygen-rich device, and the device yield, switching characteristics, and stability may be improved for silver/oxygen-doped a-Si/p+-c-Si device. Finally, the device resistive-switching mechanism was analyzed.

  • SEMICONDUCTOR MATERIALS

  • Investigation of post-thermal annealing on material properties of Cu–In–Zn–Se thin films

    H. H. Güllü, M. Parlak

    J. Semicond.  2017, 38(12): 123001

    doi: 10.1088/1674-4926/38/12/123001

    Abstract Full Text PDF Get Citation

    The Cu–In–Zn–Se thin film was synthesized by changing the contribution of In in chalcopyrite CuInSe2 with Zn. The XRD spectra of the films showed the characteristic diffraction peaks in a good agreement with the quaternary Cu–In–Zn–Se compound. They were in the polycrystalline nature without any post-thermal process, and the main orientation was found to be in the (112) direction with tetragonal crystalline structure. With increasing annealing temperature, the peak intensities in preferred orientation became more pronounced and grain sizes were in increasing behavior from 6.0 to 25.0 nm. The samples had almost the same atomic composition of Cu0.5In0.5ZnSe2. However, EDS results of the deposited films indicated that there was Se re-evaporation and/or segregation with the annealing in the structure of the film. According to the optical analysis, the transmittance values of the films increased with the annealing temperature. The absorption coefficient of the films was calculated as around 105 cm−1 in the visible region. Moreover, optical band gap values were found to be changing in between 2.12 and 2.28 eV depending on annealing temperature. The temperature-dependent dark- and photo-conductivity measurements were carried out to investigate the electrical characteristics of the films.

  • Fabrication and modeling of multi-layer metal–insulator-metal capacitors

    R Karthik, A Akshaykranth

    J. Semicond.  2017, 38(12): 123002

    doi: 10.1088/1674-4926/38/12/123002

    Abstract Full Text PDF Get Citation

    This paper presents the fabrication and modeling for capacitance–voltage characteristics of multi-layer metal–insulator–metal capacitors. It is observed that, due the applied electric field, the effective dielectric constant of the stack was increased due to the accumulation of charges at the interface of high-to-low conductance materials. It is observed that the Maxwell–Wagner polarization is dominant at low frequencies (<10 kHz). By introducing carrier tunneling probability of the dielectric stack, the model presented in this paper shows a good agreement with experimental results. The presented model indicates that the nonlinearity can be suppressed by choosing the similar permittivity dielectric materials for fabrication of multilayer metal insulator metal capacitors.

  • SEMICONDUCTOR DEVICES

  • Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

    S Chakraborty, A Dasgupta, R Das, M Kar, A Kundu, C K Sarkar

    J. Semicond.  2017, 38(12): 124001

    doi: 10.1088/1674-4926/38/12/124001

    Abstract Full Text PDF Get Citation

    In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET.

  • Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

    Manoj Kumar, Yogesh Pratap, Subhasis Haldar, Mridula Gupta, R. S. Gupta

    J. Semicond.  2017, 38(12): 124002

    doi: 10.1088/1674-4926/38/12/124002

    Abstract Full Text PDF Get Citation

    In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The ION/IOFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

  • Design and optimization analysis of dual material gate on DG-IMOS

    Sarabdeep Singh, Ashish Raman, Naveen Kumar

    J. Semicond.  2017, 38(12): 124003

    doi: 10.1088/1674-4926/38/12/124003

    Abstract Full Text PDF Get Citation

    An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG (dual material gate) DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better ION, ION/IOFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized performance is achieved including ION/IOFF ratio of 2.87 × 109 A/μm with ION as 11.87 × 10−4 A/μm and transconductance of 1.06×10−3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

  • Optical properties of Zn-diffused InP layers for the planar-type InGaAs/InP photodetectors

    Guifeng Chen, Mengxue Wang, Wenxian Yang, Ming Tan, Yuanyuan Wu, Pan Dai, Yuyang Huang, Shulong Lu

    J. Semicond.  2017, 38(12): 124004

    doi: 10.1088/1674-4926/38/12/124004

    Abstract Full Text PDF Get Citation

    Zn diffusion into InP was carried out ex-situ using a new Zn diffusion technique with zinc phosphorus particles placed around InP materials as zinc source in a semi-closed chamber formed by a modified diffusion furnace. The optical characteristics of the Zn-diffused InP layer for the planar-type InGaAs/InP PIN photodetectors grown by molecular beam epitaxy (MBE) has been investigated by photoluminescence (PL) measurements. The temperature-dependent PL spectrum of Zn-diffused InP samples at different diffusion temperatures showed that band-to-acceptor transition dominates the PL emission, which indicates that Zn was commendably diffused into InP layer as the acceptor. High quality Zn-diffused InP layer with typically smooth surface was obtained at 580 °C for 10 min. Furthermore, more interstitial Zn atoms were activated to act as acceptors after a rapid annealing process. Based on the above Zn-diffusion technique, a 50 μm planar-type InGaAs/InP PIN photodector device was fabricated and exhibited a low dark current of 7.73 pA under a reverse bias potential of −5 V and a high breakdown voltage of larger than 41 V (I < 10 μA). In addition, a high responsivity of 0.81 A/W at 1.31 μm and 0.97 A/W at 1.55 μm was obtained in the developed PIN photodetector.

  • Design of a cylindrical LED substrate without radiator

    Fan Tang, Zhenning Guo

    J. Semicond.  2017, 38(12): 124005

    doi: 10.1088/1674-4926/38/12/124005

    Abstract Full Text PDF Get Citation

    To reduce the weight and production costs of light-emitting diode (LED) lamps, we applied the principle of the chimney effect to design a cylindrical LED substrate without a radiator. We built a 3D model by using Solidworks software and applied the flow simulation plug-in to conduct model simulation, thereby optimizing the heat source distribution and substrate thickness. The results indicate that the design achieved optimal cooling with a substrate with an upper extension length of 35 mm, a lower extension length of 8 mm, and a thickness of 1 mm. For a substrate of those dimensions, the highest LED chip temperature was 64.78 °C, the weight of the substrate was 35.09 g, and Rjb = 7.00 K/W. If the substrate is powered at 8, 10, and 12 W, its temperature meets LED safety requirements. In physical tests, the highest temperature for a physical 8 W cylindrical LED substrate was 66 °C, which differed by only 1.22 °C from the simulation results, verifying the validity of the simulation. The designed cylindrical LED substrate can be used in high-power LED lamps that do not require radiators. This design is not only excellent for heat dissipation, but also for its low weight, low cost, and simplicity of manufacture.

  • SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

    Zhaohuan Tang, Xinghua Fu, Fashun Yang, Kaizhou Tan, Kui Ma, Xue Wu, Jiexing Lin

    J. Semicond.  2017, 38(12): 124006

    doi: 10.1088/1674-4926/38/12/124006

    Abstract Full Text PDF Get Citation

    Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture (SEGR) and single event burnout (SEB), which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOSFETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers. Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV·cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

    Jiafeng Wang, Xiangning Fan, Xiaoyang Shi, Zhigong Wang

    J. Semicond.  2017, 38(12): 125001

    doi: 10.1088/1674-4926/38/12/125001

    Abstract Full Text PDF Get Citation

    With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source-coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. Δ–Σ modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18μm CMOS process, the fractional-N frequency divider occupies a chip area of 1130 × 510 μm2 and it can correctly divide within the frequency range of 0.8–9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.

  • SEMICONDUCTOR TECHNOLOGY

  • All-optical temporal fractional order differentiator using an in-fiber ellipsoidal air-microcavity

    Lihong Zhang, Shuqian Sun, Ming Li, Ninghua Zhu

    J. Semicond.  2017, 38(12): 126001

    doi: 10.1088/1674-4926/38/12/126001

    Abstract Full Text PDF Get Citation

    An all-optical temporal fractional order differentiator with ultrabroad bandwidth (~1.6 THz) and extremely simple fabrication is proposed and experimentally demonstrated based on an in-fiber ellipsoidal air-microcavity. The ellipsoidal air-microcavity is fabricated by splicing a single mode fiber (SMF) and a photonic crystal fiber (PCF) together using a simple arc-discharging technology. By changing the arc-discharging times, the propagation loss can be adjusted and then the differentiation order is tuned. A nearly Gaussian-like optical pulse with 3 dB bandwidth of 8 nm is launched into the differentiator and a 0.65 order differentiation of the input pulse is achieved with a processing error of 2.55%.

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