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Volume 38, Issue 8, Aug 2017

# SEMICONDUCTOR PHYSICS

• ## ZnO1-xTex and ZnO1-xSx semiconductor alloys as competent materials for opto-electronic and solar cell applications:a comparative analysis

J. Semicond.  2017, 38(8): 082001

doi: 10.1088/1674-4926/38/8/082001

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ZnO1-xTex ternary alloys have great potential to work as a photovoltaic (PV) absorber in solar cells. ZnO1-xSx is also a ZnO based alloy that have uses in solar cells. In this paper we report the comparative study of various parameters of ZnO1-xTex and ZnO1-xSx for selecting it to be a competent material for solar cell applications. The parameters are mainly being calculated using the well-known VCA (virtual crystal approximation) and VBAC (Valence Band Anti-Crossing) model. It was certainly being analysed that the incorporation of Te atoms produces a high band gap lower than S atoms in the host ZnO material. The spin-orbit splitting energy value of ZnO1-xTex was found to be higher than that of ZnO1-xSx. Beside this, the strain effects are also higher in ZnO1-xTex than ZnO1-xSx. The remarkable notifying result which the paper is reporting is that at a higher percentage of Te atoms in ZnO1-xTex, the spin-orbit splitting energy value rises above the band gap value, which signifies a very less internal carrier recombination that decreases the leakage current and increases the efficiency of the solar cell. Moreover, it also covers a wide wavelength range compared to ZnO1-xSx.

• ## Controllable persistent spin-polarized charge current in a Rashba ring

J. Semicond.  2017, 38(8): 082002

doi: 10.1088/1674-4926/38/8/082002

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We theoretically predict the appearance of a persistent charge current in a Rashba ring with a normal and a ferromagnetic lead under no external bias. This charge current is the result of the breaking of the time inversion symmetry in the original persistent pure spin current induced by the Rashba spin-orbit coupling (RSOC) in the ring due to the existence of the ferromagnetic lead. With the Keldysh Green's function technique, we find that not only the magnitude and sign but also the spin polarization of the generated charge current is determined by the system parameters such as the magnetization direction of the ferromagnetic lead, the tunneling coefficient, the strength of the RSOC and the exchange energy of the ferromagnetic lead, which are all tunable in experiments, that is, a controllable persistent spin-polarized charge current can be obtained in such a device.

• # SEMICONDUCTOR MATERIALS

• ## First-principles study of p-type ZnO by S-Na co-doping

J. Semicond.  2017, 38(8): 083001

doi: 10.1088/1674-4926/38/8/083001

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Using the first-principles method based on the density functional theory, the formation energy, electronic structures of S-Na co-doping in ZnO were calculated. The calculated results show that NaZn-SO have smaller formation energy than Nain-SO in energy ranges from -3.10 to 0 eV of μO, indicating that it opens up a new opportunity for growth the p-type ZnO. The band structure shows that the NaZn system is a p-type direct-band-gap semiconductor material and the calculated band gap (0.84 eV) is larger than pure ZnO (0.74 eV). The NaZn-SO system is also a p-type semiconductor material with a direct band gap (0.80 eV). The influence of S-Na co-doping in ZnO on p-type conductivity is also discussed. The effective masses of NaZn-SO are larger than effective masses of NaZn and the NaZn-SO have more hole carriers than NaZn, meaning the hole in the NaZn-SO system may have a better carrier transfer character. So we inferred that NaZn-SO should be a candidate of p-type conduction.

• ## Comparative study on the influence of Al component at GaAlAs layer for GaAs/AlGaAs photocathode

J. Semicond.  2017, 38(8): 083002

doi: 10.1088/1674-4926/38/8/083002

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We designed two transmission-mode GaAs/AlGaAs photocathodes with different AlxGa1-xAs layers, one has an AlxGa1-xAs layer with the Al component ranging from 0.9 to 0, and the other has a fixed Al component 0.7. Using the first-principle method, we calculated the electronic structure and absorption spectrum of AlxGa1-xAs at x=0, 0.25, 0.5, 0.75 and 1, calculation results suggest that with the increase of the Al component, the band gap of AlxGa1-xAs increases. Then we activated the two samples, and obtained the spectral response curves and quantum efficiency curves; it is found that sample 1 has a better shortwave response and higher quantum efficiency at short wavelengths. Combined with the band structure diagram of the transmission-mode GaAs/AlGaAs photocathode and the fitted performance parameters, we analyze the phenomenon. It is found that the transmission-mode GaAs/AlGaAs photocathode with variable Al component and various doping structure can form a two-stage built-in electric field, which improves the probability of shortwave response photoelectrons escaping to the vacuum. In conclusion, such a structure reduces the influence of back-interface recombination, improves the shortwave response of the transmission-mode photocathode.

• # SEMICONDUCTOR DEVICES

• ## 30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substrates for future high power RF applications

J. Semicond.  2017, 38(8): 084001

doi: 10.1088/1674-4926/38/8/084001

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The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance gm of 1050 mS/mm, current gain cut-off frequency ft of 350 GHz and power gain cut-off frequency fmax of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density (ns) and breakdown voltage are 1580 cm2/(V·s), 1.9×1013 cm-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.

• ## Statistically modeling I-V characteristics of CNT-FET with LASSO

J. Semicond.  2017, 38(8): 084002

doi: 10.1088/1674-4926/38/8/084002

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With the advent of internet of things (IOT), the need for studying new material and devices for various applications is increasing. Traditionally we build compact models for transistors on the basis of physics. But physical models are expensive and need a very long time to adjust for non-ideal effects. As the vision for the application of many novel devices is not certain or the manufacture process is not mature, deriving generalized accurate physical models for such devices is very strenuous, whereas statistical modeling is becoming a potential method because of its data oriented property and fast implementation. In this paper, one classical statistical regression method, LASSO, is used to model the I-V characteristics of CNT-FET and a pseudo-PMOS inverter simulation based on the trained model is implemented in Cadence. The normalized relative mean square prediction error of the trained model versus experiment sample data and the simulation results show that the model is acceptable for digital circuit static simulation. And such modeling methodology can extend to general devices.

• ## Resistive switching characteristic of electrolyte-oxide-semiconductor structures

J. Semicond.  2017, 38(8): 084003

doi: 10.1088/1674-4926/38/8/084003

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The resistive switching characteristic of SiO2 thin film in electrolyte-oxide-semiconductor (EOS) structures under certain bias voltage is reported. To analyze the mechanism of the resistive switching characteristic, a batch of EOS structures were fabricated under various conditions and their electrical properties were measured with a set of three-electrode systems. A theoretical model based on the formation and rupture of conductive filaments in the oxide layer is proposed to reveal the mechanism of the resistive switching characteristic, followed by an experimental investigation of Auger electron spectroscopy (AES) and secondary ion mass spectroscopy (SIMS) to verify the proposed theoretical model. It is found that different threshold voltage, reverse leakage current and slope value features of the switching I-V characteristic can be observed in different EOS structures with different electrolyte solutions as well as different SiO2 layers made by different fabrication processes or in different thicknesses. With a simple fabrication process and significant resistive switching characteristic, the EOS structures show great potential for chemical/biochemical applications.

• ## Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

J. Semicond.  2017, 38(8): 084004

doi: 10.1088/1674-4926/38/8/084004

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The effects of different NH3-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH3-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79×1011 eV-1cm-2 and low gate leakage current (3.43×10-5A/cm2 at Vg=1 V) could be achieved for the sample with NH3-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH3-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeOxNy, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeOx interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH3-plasma.

• ## Fabrication and characteristics of excellent current spreading GaN-based LED by using transparent electrode-insulator-semiconductor structure

J. Semicond.  2017, 38(8): 084005

doi: 10.1088/1674-4926/38/8/084005

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GaN-based vertical light-emitting-diodes (V-LEDs) with an improved current injection pattern were fabricated and a novel current injection pattern of LEDs which consists of electrode-insulator-semiconductor (EIS) structure was proposed. The EIS structure was achieved by an insulator layer (20-nm Ta2O5) deposited between the p-GaN and the ITO layer. This kind of EIS structure works through a defect-assisted tunneling mechanism to realize current injection and obtains a uniform current distribution on the chip surface, thus greatly improving the current spreading ability of LEDs. The appearance of this novel current injection pattern of V-LEDs will subvert the impression of the conventional LEDs structure, including simplifying the chip manufacture technology and reducing the chip cost. Under a current density of 2, 5, 10, and 25 A/cm2, the luminous uniformity was better than conventional structure LEDs. The standard deviation of power density distribution in light distribution was 0.028, which was much smaller than that of conventional structure LEDs and illustrated a huge advantage on the current spreading ability of EIS-LEDs.

• ## Theoretical simulation of performances in CIGS thin-film solar cells with cadmium-free buffer layer

J. Semicond.  2017, 38(8): 084006

doi: 10.1088/1674-4926/38/8/084006

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Copper indium gallium selenium (CIGS) thin film solar cells have become one of the hottest topics in solar energy due to their high photoelectric transformation efficiency. To real applications, CIGS thin film is covered by the buffer layer and absorption layer. Traditionally, cadmium sulfide (CdS) is inserted into the middle of the window layer (ZnO) and absorption layer (CIGS) as a buffer layer. However, the application of the GIGS/CdS thin film solar cells has been limited because of the environmental pollution resulting from the toxic cadmium atom. Although zinc sulfide (ZnS) has been proposed to be one of the candidates, the performance of such battery cells has not been investigated. Here, in this paper, we systematically study the possibility of using zinc sulfide (ZnS) as a buffer layer. By including the effects of thickness, concentration of a buffer layer, intrinsic layer and the absorbing layer, we find that photoelectric transformation efficiency of ZnO/ZnS(n)/CIGS(i)/CIGS(p) solar cell is about 17.22%, which is qualified as a commercial solar cell. Moreover, we also find that the open-circuit voltage is~0.60 V, the short-circuit current is~36.99 mA/cm2 and the filled factor is~77.44%. Therefore, our results suggest that zinc sulfide may be the potential candidate of CdS as a buffer layer.

• # SEMICONDUCTOR INTEGRATED CIRCUITS

• ## A 75 GHz regenerative dynamic frequency divider with active transformer using InGaAs/InP HBT technology

J. Semicond.  2017, 38(8): 085001

doi: 10.1088/1674-4926/38/8/085001

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This letter presents a high speed 2:1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7 μm InP DHBT technology with fT of 165 GHz and fmax of 230 GHz. The circuit includes a two-stage active transformer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer (widely known as the Gilbert cell) and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469×414 μm2 and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximum output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.

• ## A high-speed power detector MMIC for E-band communication

J. Semicond.  2017, 38(8): 085002

doi: 10.1088/1674-4926/38/8/085002

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An E-band high speed power detector MMIC using 0.1 μm pHEMT technology has been designed, manufactured and experimentally characterized. By employing a 4-way quadrature structure for phase cancellation, the first, second and third harmonics can be suppressed and the ripple at the output is minimized. Compared to conventional topology with a low pass filter, a short response time and high speed performance of demodulation can be reached. Simulated results indicate that the detector is capable of demodulating an on-off keying signal at a data rate up to 5 Gbps. The fabricated chip occupies 1×1.5 mm2 and the on-wafer measurement shows a return loss of less than -15 dB, responsivity better than 700 mV/mW and dynamic range of more than 25 dB over 70 to 90 GHz.

• ## A 500-600 MHz GaN power amplifier with RC-LC stability network

J. Semicond.  2017, 38(8): 085003

doi: 10.1088/1674-4926/38/8/085003

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A 500-600 MHz high-efficiency, high-power GaN power amplifier is designed and realized on the basis of the push-pull structure. The RC-LC stability network is proposed and applied to the power amplifier circuit for the first time. The RC-LC stability network can significantly reduce the high gain out the band, which eliminates the instability of the power amplifier circuit. The developed power amplifier exhibits 58.5 dBm (700 W) output power with a 17 dB gain and 85% PAE at 500-600 MHz, 300 μs, 20% duty cycle. It has the highest PAE in P-band among the products at home and abroad.

• ## The design of miniaturized broadband power divider utilizing GaAs-based IPD process and equivalent circuit model

J. Semicond.  2017, 38(8): 085004

doi: 10.1088/1674-4926/38/8/085004

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The GaAs-based TF-IPD fabrication process and equivalent lumped element circuit are utilized to reduce the circuit size for double-section Wilkinson power divider. Ultimately the dimension of the proposed S-band power divider is reduced to 1.03×0.98 mm2. Its measured results show an operating fractional bandwidth of 54%, and return losses and isolation of greater than 20 dB. In addition the excess insertion loss is less than 1.1 dB. Moreover the good features contain amplitude and phase equilibrium with the values of better than 0.03 dB and 1.5° separately. This miniaturized power divider could be widely used in RF/microwave circuit systems.

• ## An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

J. Semicond.  2017, 38(8): 085005

doi: 10.1088/1674-4926/38/8/085005

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This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

• ## A high sensitive 66 dB linear dynamic range receiver for 3-D laser radar

J. Semicond.  2017, 38(8): 085006

doi: 10.1088/1674-4926/38/8/085006

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This study presents a CMOS receiver chip realized in 0.18 μm standard CMOS technology and intended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode transimpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 kΩ, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB (1:2000), and the input referred noise current is 2.3 pA/$\sqrt {{\rm{Hz}}}$ (rms), resulting in a very low detectable input current of 1 μ A with SNR=5.

• ## On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

J. Semicond.  2017, 38(8): 085007

doi: 10.1088/1674-4926/38/8/085007

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This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μ W, while the digital part consumes only 203 μ W.

• ## A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

J. Semicond.  2017, 38(8): 085008

doi: 10.1088/1674-4926/38/8/085008

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A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm2, where the active area of the transmitter block is 0.5×1.2 mm2.

• ## Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

J. Semicond.  2017, 38(8): 085009

doi: 10.1088/1674-4926/38/8/085009

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With the critical charge reduced to generate a single event effect (SEE) and high working frequency for a nanometer integrated circuit, the single event effect (SET) becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n+ guard ring and p+ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient (SET) pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET's pulse-width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV·cm2/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETeff from 12.5 MeV·cm2/mg to 79.5 MeV·cm2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer (LETeff) value is larger than 40 MeV·cm2/mg. The test results also show that the hardened commercial standard cell's pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.