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Volume 39, Issue 3, Mar 2018

    SEMICONDUCTOR MATERIALS

  • Synthesis and characterization of ZnO–CuO nanocomposites powder by modified perfume spray pyrolysis method and its antimicrobial investigation

    D. Saravanakkumar, S. Sivaranjani, K. Kaviyarasu, A. Ayeshamariam, B. Ravikumar, S. Pandiarajan, C. Veeralakshmi, M. Jayachandran, M. Maaza

    J. Semicond.  2018, 39(3): 033001

    doi: 10.1088/1674-4926/39/3/033001

    Abstract Full Text PDF Get Citation

    Pure ZnO, ZnO–CuO nanocomposites can be synthesized by using a modified perfume spray pyrolysis method (MSP). The crystallite size of the nanoparticles (NPs) has been observed by X-ray diffraction pattern and is nearly 36 nm. Morphological studies have been analyzed by using Field Emission Scanning Electron Microscopy (FESEM) and its elemental analysis was reported by Elemental X-ray Analysis (EDX); these studies confirmed that ZnO and CuO have hexagonal structure and monoclinic structure respectively. Fourier Transform Infrared (FTIR) spectra revealed that the presence of functional frequencies of ZnO and CuO were observed at 443 and 616 cm−1. The average bandgap value at 3.25 eV using UV–vis spectra for the entitled composite has described a blue shift that has been observed here. The antibacterial study against both gram positive and negative bacteria has been studied by the disc diffusion method. To the best of our knowledge, it is the first report on ZnO–CuO nanocomposite synthesized by a modified perfume spray pyrolysis method.

  • Gas selectivity of SILAR grown CdS nano-bulk junction

    R. Jayakrishnan, Varun G Nair, Akhil M Anand, Meera Venugopal

    J. Semicond.  2018, 39(3): 033002

    doi: 10.1088/1674-4926/39/3/033002

    Abstract Full Text PDF Get Citation

    Nano-particles of cadmium sulphide were deposited on cleaned copper substrate by an automated sequential ionic layer adsorption reaction (SILAR) system. The grown nano-bulk junction exhibits Schottky diode behavior. The response of the nano-bulk junction was investigated under oxygen and hydrogen atmospheric conditions. The gas response ratio was found to be 198% for Oxygen and 34% for Hydrogen at room temperature. An increase in the operating temperature of the nano-bulk junction resulted in a decrease in their gas response ratio. A logarithmic dependence on the oxygen partial pressure to the junction response was observed, indicating a Temkin isothermal behavior. Work function measurements using a Kelvin probe demonstrate that the exposure to an oxygen atmosphere fails to effectively separate the charges due to the built-in electric field at the interface. Based on the benefits like simple structure, ease of fabrication and response ratio the studied device is a promising candidate for gas detection applications.

  • Investigation on the InAs1–xSbx epilayers growth on GaAs (001) substrate by molecular beam epitaxy

    D. Benyahia, Ł. Kubiszyn, K. Michalczewski, A. Kębłowski, P. Martyniuk, J. Piotrowski, A. Rogalski

    J. Semicond.  2018, 39(3): 033003

    doi: 10.1088/1674-4926/39/3/033003

    Abstract Full Text PDF Get Citation

    Undoped and Be-doped InAs1–xSbx (0 ≤ x ≤ 0.71) epitaxial layers were successfully grown on lattice mismatched semi-insulating GaAs (001) substrate with 2° offcut towards <110>. The effect of the InAs buffer layer on the quality of the grown layers was investigated. Moreover, the influence of Sb/In flux ratio on the Sb fraction was examined. Furthermore, we have studied the defects distribution along the depth of the InAsSb epilayers. In addition, the p-type doping of the grown layers was explored. The InAsSb layers were assessed by X-ray diffraction, Nomarski microscopy, high resolution optical microscopy and Hall effect measurement. The InAs buffer layer was found to be beneficial for the growth of high quality InAsSb layers. The X-ray analysis revealed a full width at half maximum (FWHM) of 571 arcsec for InAs 0.87Sb0.13. It is worth noting here that the Hall concentration (mobility) as low (high) as 5 × 1016 cm−3 (25000 cm2V−1s−1) at room temperature, has been acquired.

  • Studies on morphology, electrical and optical characteristics of Al-doped ZnO thin films grown by atomic layer deposition

    Li Chen, Xinliang Chen, Zhongxin Zhou, Sheng Guo, Ying Zhao, Xiaodan Zhang

    J. Semicond.  2018, 39(3): 033004

    doi: 10.1088/1674-4926/39/3/033004

    Abstract Full Text PDF Get Citation

    Al doped ZnO (AZO) films deposited on glass substrates through the atomic layer deposition (ALD) technique are investigated with various temperatures from 100 to 250 °C and different Zn : Al cycle ratios from 20 : 0 to 20 : 3. Surface morphology, structure, optical and electrical properties of obtained AZO films are studied in detail. The Al composition of the AZO films is varied by controlling the ratio of Zn : Al. We achieve an excellent AZO thin film with a resistivity of 2.14 × 10−3 Ω·cm and high optical transmittance deposited at 150 °C with 20 : 2 Zn : Al cycle ratio. This kind of AZO thin films exhibit great potential for optoelectronics device application.

  • Efficient dye-sensitized solar cells from mesoporous zinc oxide nanostructures sensitized by N719 dye

    G. R. A. Kumara, U. Deshapriya, C. S. K. Ranasinghe, E. N. Jayaweera, R. M. G. Rajapakse

    J. Semicond.  2018, 39(3): 033005

    doi: 10.1088/1674-4926/39/3/033005

    Abstract Full Text PDF Get Citation

    Dye-sensitized solar cells (DSCs) have attracted a great deal of attention due to their low-cost and high power conversion efficiencies. They usually utilize an interconnected nanoparticle layer of TiO2 as the electron transport medium. From the fundamental point of view, faster mobility of electrons in ZnO is expected to contribute to better performance in DSCs than TiO2, though the actual practical situation is quite the opposite. In this research, we addressed this problem by first applying a dense layer of ZnO on FTO followed by a mesoporous layer of interconnected ZnO nanoparticle layer, both were prepared by spray pyrolysis technique. The best cell shows a power conversion efficiency of 5.2% when the mesoporous layer thickness is 14 μm and the concentration of the N719 dye in dye coating solution is 0.3 mM, while a cell without a dense layer shows 4.2% under identical conditions. The surface concentration of dye adsorbed in the cell with a dense layer and that without a dense layer are 5.00 × 10−7 and 3.34 × 10−7 mol/cm2, respectively. The cell with the dense layer has an electron lifetime of 54.81 ms whereas that without the dense layer is 11.08 ms. As such, the presence of the dense layer improves DSC characteristics of ZnO-based DSCs.

  • Analysis of the growth of GaN epitaxy on silicon

    Danmei Zhao, Degang Zhao

    J. Semicond.  2018, 39(3): 033006

    doi: 10.1088/1674-4926/39/3/033006

    Abstract Full Text PDF Get Citation

    Due to the great potential of GaN based devices, the analysis of the growth of crack-free GaN with high quality has always been a research hotspot. In this paper, two methods for improving the property of the GaN epitaxial layer on Si (111) substrate are researched. Sample A, as a reference, only has an AlN buffer between the Si substrate and the epitaxy. In the following two samples, a GaN transition layer (sample B) and an AlGaN buffer (sample C) are grown on the AlN buffer separately. Both methods improve the quality of GaN. Meanwhile, using the second method, the residual tensile thermal stress decreases. To further study the impact of the two introduced layers, we investigate the stress condition of GaN epitaxial layer by Raman spectrum. According to the Raman spectrum, the calculated residual stress in the GaN epitaxial layer is approximately 0.72 GPa for sample B and 0.42 GPa for sample C. The photoluminescence property of GaN epitaxy is also investigated by room temperature PL spectrum.

  • SEMICONDUCTOR DEVICES

  • Room temperature continuous wave operation of quantum cascade laser at λ ~ 9.4 μm

    Chuncai Hou, Yue Zhao, Jinchuan Zhang, Shenqiang Zhai, Ning Zhuo, Junqi Liu, Lijun Wang, Shuman Liu, Fengqi Liu, Zhanguo Wang

    J. Semicond.  2018, 39(3): 034001

    doi: 10.1088/1674-4926/39/3/034001

    Abstract Full Text PDF Get Citation

    Continuous wave (CW) operation of long wave infrared (LWIR) quantum cascade lasers (QCLs) is achieved up to a temperature of 303 K. For room temperature CW operation, the wafer with 35 stages was processed into buried heterostructure lasers. For a 2-mm-long and 10-μm-wide laser with high-reflectivity (HR) coating on the rear facet, CW output power of 45 mW at 283 K and 9 mW at 303 K is obtained. The lasing wavelength is around 9.4 μm locating in the LWIR spectrum range.

  • Investigation of internally finned LED heat sinks

    Bin Li, Lun Xiong, Chuan Lai, Yumei Tang

    J. Semicond.  2018, 39(3): 034002

    doi: 10.1088/1674-4926/39/3/034002

    Abstract Full Text PDF Get Citation

    A novel heat sink is proposed, which is composed of a perforated cylinder and internally arranged fins. Numerical studies are performed on the natural convection heat transfer from internally finned heat sinks; experimental studies are carried out to validate the numerical results. To compare the thermal performances of internally finned heat sinks and externally finned heat sinks, the effects of the overall diameter, overall height, and installation direction on maximum temperature, air flow and heat transfer coefficient are investigated. The results demonstrate that internally finned heat sinks show better thermal performance than externally finned heat sinks; the maximum temperature of internally finned heat sinks decreases by up to 20% compared with the externally finned heat sinks. The existence of a perforated cylinder and the installation direction of the heat sink affect the thermal performance significantly; it is shown that the heat transfer coefficient of the heat sink with the perforated cylinder is improved greater than that with the imperforated cylinder by up to 34%, while reducing the mass of the heat sink by up to 13%.

  • Single-event burnout hardening of planar power MOSFET with partially widened trench source

    Jiang Lu, Hainan Liu, Xiaowu Cai, Jiajun Luo, Bo Li, Binhong Li, Lixin Wang, Zhengsheng Han

    J. Semicond.  2018, 39(3): 034003

    doi: 10.1088/1674-4926/39/3/034003

    Abstract Full Text PDF Get Citation

    We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N+ source). The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer (LET), which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to 0.7 pC/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.

  • Cadmium sulfide thin films growth by chemical bath deposition

    S. Hariech, M. S. Aida, J. Bougdira, M. Belmahi, G. Medjahdi, D. Genève, N. Attaf, H. Rinnert

    J. Semicond.  2018, 39(3): 034004

    doi: 10.1088/1674-4926/39/3/034004

    Abstract Full Text PDF Get Citation

    Cadmium sulfide (CdS) thin films have been prepared by a simple technique such as chemical bath deposition (CBD). A set of samples CdS were deposited on glass substrates by varying the bath temperature from 55 to 75 °C at fixed deposition time (25 min) in order to investigate the effect of deposition temperature on CdS films physical properties. The determination of growth activation energy suggests that at low temperature CdS film growth is governed by the release of Cd2+ ions in the solution. The structural characterization indicated that the CdS films structure is cubic or hexagonal with preferential orientation along the direction (111) or (002), respectively. The optical characterization indicated that the films have a fairly high transparency, which varies between 55% and 80% in the visible range of the optical spectrum, the refractive index varies from 1.85 to 2.5 and the optical gap value of which can reach 2.2 eV. It can be suggested that these properties make these films perfectly suitable for their use as window film in thin films based solar cells.

  • Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

    Xiaolei Yang, Yonghong Tao, Tongtong Yang, Runhua Huang, Bai Song

    J. Semicond.  2018, 39(3): 034005

    doi: 10.1088/1674-4926/39/3/034005

    Abstract Full Text PDF Get Citation

    Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices, n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications. In this paper, backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs. The thickness of a drift layer was 120 μm, which was designed for a blocking voltage of 13 kV. The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V, with a differential specific on-resistance of 140 mΩ·cm2.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • High speed true random number generator with a new structure of coarse-tuning PDL in FPGA

    Hongzhen Fang, Pengjun Wang, Xu Cheng, Keji Zhou

    J. Semicond.  2018, 39(3): 035001

    doi: 10.1088/1674-4926/39/3/035001

    Abstract Full Text PDF Get Citation

    A metastability-based TRNG (true random number generator) is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL (programmable delay line). With the proposed coarse-tuning PDL structure, the TRNG core does not require extra placement and routing to ensure its entropy. Furthermore, the core needs fewer stages of coarse-tuning PDL at higher operating frequency, and thus saves more resources in FPGA. The designed TRNG achieves 25 Mbps @ 100 MHz throughput after proper post-processing, which is several times higher than other previous TRNGs based on FPGA. Moreover, the robustness of the system is enhanced with the adoption of a feedback system. The quality of the designed TRNG is verified by NIST (National Institute of Standards and Technology) and also accepted by class P1 of the AIS-20/31 test suite.

  • An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

    Xin Cheng, Yu Zhang, Guangjun Xie, Yizhong Yang, Zhang Zhang

    J. Semicond.  2018, 39(3): 035002

    doi: 10.1088/1674-4926/39/3/035002

    Abstract Full Text PDF Get Citation

    An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE) circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA. The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV. Moreover, the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.

  • Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer

    Yutong Ying, Fujiang Lin, Xuefei Bai

    J. Semicond.  2018, 39(3): 035003

    doi:  10.1088/1674-4926/39/3/035003

    Abstract Full Text PDF Get Citation

    This paper explores an energy-efficient pulsed ultra-wideband (UWB) radio-frequency (RF) front-end chip fabricated in 0.18-μm CMOS technology, including a transmitter, receiver, and fractional synthesizer. The transmitter adopts a digital offset quadrature phase-shift keying (O-QPSK) modulator and passive direct-phase multiplexing technology, which are energy- and hardware-efficient, to enhance the data rate for a given spectrum. A passive mixer and a capacitor cross-coupled (CCC) source-follower driving amplifier (DA) are also designed for the transmitter to further reduce the low power consumption. For the receiver, a power-aware low-noise amplifier (LNA) and a quadrature mixer are applied. The LNA adopts a CCC boost common-gate amplifier as the input stage, and its current is reused for the second stage to save power. The mixer uses a shared amplification stage for the following passive IQ mixer. Phase noise suppression of the phase-locked loop (PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator (QVCO) and an in-band noise-aware charge pump (CP) design. The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 mW and 31.5 mW for the transmitter and the receiver, respectively. The optimized integrated phase noise of the PLL is 0.52° at 4.025 GHz.

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