J. Semicond. > Volume 31 > Issue 1 > Article Number: 014003

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

Zhu Jing , Qian Qinsong , Sun Weifeng and Liu Siyang

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Abstract: The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power transistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

Key words: electrostatic discharge

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Zhu J, Qian Q S, Sun W F, Liu S Y. Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress[J]. J. Semicond., 2010, 31(1): 014003. doi: 10.1088/1674-4926/31/1/014003.

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History

Manuscript received: 18 August 2015 Manuscript revised: 07 August 2009 Online: Published: 01 January 2010

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