J. Semicond. > Volume 34 > Issue 6 > Article Number: 065005

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

Zhenhai Chen 1, 2, , , Hongwen Qian 2, , Songren Huang 1, 2, , Hong Zhang 3, and Zongguang Yu 1, 2,

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Abstract: A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/-0.4 LSB and integral nonlinearity (INL) is +0.8/-0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.

Key words: time-interleavedpipelined analog-to-digital convertercharge domainlow powerbootstrapped sampling switchdelay locked loop

Abstract: A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/-0.4 LSB and integral nonlinearity (INL) is +0.8/-0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.

Key words: time-interleavedpipelined analog-to-digital convertercharge domainlow powerbootstrapped sampling switchdelay locked loop



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Xu Lai, Yin Xiumei, Yang Huazhong. A 10-bit 100 Msps low power time-interleaved ADC using OTA sharing[J]. Journal of Semiconductors, 2010, 31(9): 095012. doi: 10.1088/1674-4926/31/9/095012

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[1]

Black W C, Hodges D A. Time interleaved converter arrays[J]. IEEE J Solid-State Circuits, 1980, 15(6): 1022. doi: 10.1109/JSSC.1980.1051512

[2]

Arias J, Boccuzzi V, Quintanilla L. Low-power pipeline ADC for wireless LANs[J]. IEEE J Solid-State Circuits, 2004, 39(8): 1338. doi: 10.1109/JSSC.2004.831477

[3]

Min B M, Kim P, Bowman F W. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC[J]. IEEE J Solid-State Circuits, 2003, 38(12): 2031. doi: 10.1109/JSSC.2003.819166

[4]

Hsu C C, Huang F C, Shih C Y. An 11 b 800 MS/s time-interleaved ADC with digital background calibration[J]. IEEE ISSCC Dig Tech Papers, 2007: 464.

[5]

Law C H, Hurst P J, Lewis S H. A four-channel time-interleaved ADC with digital calibration of inter-channel timing and memory errors[J]. IEEE J Solid-State Circuits, 2010, 45(10): 2091. doi: 10.1109/JSSC.2010.2061630

[6]

Buchanan J E. Bucket brigade analog-to-digital converter[J]. US Patent, No. 4072938, 1978.

[7]

Anthony M, Kohler E, Kurtze J. A process-scalable low-power charge-domain 13-bit pipeline ADC[J]. Symposium on VLSI Circuits, 2008: 222.

[8]

Anthony M, Kurtze J. Charge domain pipelined analog to digital converter[J]. US Patent, No. 7570192, 2009.

[9]

Chen Z H, Yu Z G, Huang S R.. A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs[J]. IEICE Electron Express, 2012, 9(6): 565. doi: 10.1587/elex.9.565

[10]

Liang C K, Yang R J, Liu S I. An all-digital fast-locking programmable DLL-based clock generator[J]. IEEE Trans Circuits Syst I:Regular Papers, 2008, 55(1): 361. doi: 10.1109/TCSI.2007.913612

[11]

Abo A M, Gray P R. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter[J]. IEEE J Solid-State Circuits, 1999, 34(5): 599. doi: 10.1109/4.760369

[12]

Hu X Y, Zhou Y M. A CMOS sampling switch for 14 bit 50 MHz pipelined A/D converter[J]. Chinese Journal of Semiconductors, 2007, 28(9): 1808.

[13]

Aksin D, Al-Shyoukh M, Maloberti F. Switch bootstrapping for precise sampling beyond supply voltage[J]. IEEE J Solid-State Circuits, 2006, 41(8): 1938. doi: 10.1109/JSSC.2006.875305

[14]

Xu Lai, Yin Xiumei, Yang Huazhong. A 10-bit 100 Msps low power time-interleaved ADC using OTA sharing[J]. Journal of Semiconductors, 2010, 31(9): 095012. doi: 10.1088/1674-4926/31/9/095012

[15]

Chu J, Lee H S. A 450 MS/s 10-bit time-interleaved zero-crossing based ADC[J]. IEEE Custom Integrated Circuits Conference, 2011: 1.

[16]

Kim Y H, Lee J, Cho S H. A 10-bit 300 MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages[J]. IEEE International Symposium on Circuits and Systems, 2010: 4041.

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Z H Chen, H W Qian, S R Huang, H Zhang, Z G Yu. A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling[J]. J. Semicond., 2013, 34(6): 065005. doi: 10.1088/1674-4926/34/6/065005.

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History

Manuscript received: 11 October 2012 Manuscript revised: 19 January 2013 Online: Published: 01 June 2013

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