J. Semicond. > Volume 35 > Issue 8 > Article Number: 085001

Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

Jia Zhang 1, 2, , Haigang Yang 1, , , Jiabin Sun 1, , Le Yu 1, and Yuanfeng Wei 1,

+ Author Affilications + Find other works by these authors

PDF

Abstract: This paper proposes a novel technique for modeling the electrostatic discharge (ESD) characteristic of the enclosed-gate layout transistors (ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELT is decomposed into edge and corner transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM (Berkeley Short-channel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.

Key words: Electrostatic dischargeEnclosed-gate layout transistormodelingconformal mapping

Abstract: This paper proposes a novel technique for modeling the electrostatic discharge (ESD) characteristic of the enclosed-gate layout transistors (ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELT is decomposed into edge and corner transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM (Berkeley Short-channel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.

Key words: Electrostatic dischargeEnclosed-gate layout transistormodelingconformal mapping



References:

[1]

Lee M S, Lee H C. Dummy gate-assisted n-MOSFET layout for a radiation-tolerant integrated circuit[J]. IEEE Trans Nucl Sci, 2013, 60(4): 3084. doi: 10.1109/TNS.2013.2268390

[2]

Nowlin R, McEndree S, Wilson A. A new total-dose-induced parasitic effect in enclosed-geometry transistors[J]. IEEE Trans Nucl Sci, 2005, 52(6): 2495. doi: 10.1109/TNS.2005.860713

[3]

VSilvestri M, Gerardin S, Paccagnella A. Degradation induced by X-ray irradiation and channel hot carrier stresses in 130-nm NMOSFETs with enclosed layout[J]. IEEE Trans Nucl Sci, 2008, 55(6): 3216. doi: 10.1109/TNS.2008.2006747

[4]

Ker M D, Wu C Y, Wu T S. Area-efficient layout design for CMOS output transistors[J]. IEEE Trans Electron Devices, 1997, 44(4): 635. doi: 10.1109/16.563369

[5]

Champion C L, Rue G S L. Accurate SPICE models for CMOS analog radiation-hardness-by-design[J]. IEEE Trans Nucl Sci, 2005, 52(6): 2542. doi: 10.1109/TNS.2005.860717

[6]

Chen L, Gingrich D M. Study of n-channel MOSFETs with an enclosed-gate layout in a 0.18μm CMOS technology[J]. IEEE Trans Nucl Sci, 2005, 52(4): 861. doi: 10.1109/TNS.2005.852652

[7]

Jiao C, Yu Z. A robust novel technique for SPICE simulation of ESD snapback characteristic[J]. Proceedings of the 8th International Conference on Solid-State Integrated Circuit Technology, 2006: 1367.

[8]

Vassilev V, Lorenzini M, Groeseneken G. MOSFET ESD breakdown modeling and parameter extraction in advanced CMOS technologies[J]. IEEE Trans Electron Devices, 2006, 53(9): 2108. doi: 10.1109/TED.2006.880367

[9]

Li J, Joshi S, Rosenbaum E. A verilog-a compact model for ESD protection NMOSTs[J]. Proceedings of Custom Integrated Circuits Conference, 2003: 253.

[10]

Gao X, Liou J, Bernier J. Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2002, 21(12): 1497. doi: 10.1109/TCAD.2002.804379

[11]

Zhou Y Z, Connerney D, Carroll R. Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models[J]. Proceedings of the 6th International Symposium on Quality Electronic Design, San Jose, 2005: 476.

[12]

Giraldo A, Paccagnella A, Minzoni A. Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout[J]. Solid-State Electron, 2000, 44: 981. doi: 10.1016/S0038-1101(00)00010-1

[13]

Liu W D, Jin X D, Chen J, et al. BSIM3v3. 2. 2 MOSFET model users' manual. Department of Electrical Engineering and Computer Sciences University of California, Berkeley, 1999

[14]

Van der Toorn R, Paasschens J C J, Kloosterman W J. The Mextram bipolar transistor model, level 504. 10. 1. Users' Manual, Koninklijke Philips Electronics N. V. , Amsterdam, Netherlands, 2000/2004

[15]

Chen S H, Ker M D, Hung H P. Active ESD protection design for interface circuits between separated power domains against cross-power-domain ESD stresses[J]. IEEE Trans Device Mater Reliab, 2008, 8(3): 549. doi: 10.1109/TDMR.2008.2002492

[16]

Meng K H, Rosenbaum E. Verification of snapback model by transient I-V measurement for circuit simulation of ESD response[J]. IEEE Trans Device Mater Reliab, 2013, 13(2): 371. doi: 10.1109/TDMR.2013.2258672

[17]

Amerasekera A, Ramaswamy S, Chang M. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations[J]. Proceedings of the 34th Annual IEEE International Reliability Physics Symposium, Dallas, 1996: 318.

[1]

Lee M S, Lee H C. Dummy gate-assisted n-MOSFET layout for a radiation-tolerant integrated circuit[J]. IEEE Trans Nucl Sci, 2013, 60(4): 3084. doi: 10.1109/TNS.2013.2268390

[2]

Nowlin R, McEndree S, Wilson A. A new total-dose-induced parasitic effect in enclosed-geometry transistors[J]. IEEE Trans Nucl Sci, 2005, 52(6): 2495. doi: 10.1109/TNS.2005.860713

[3]

VSilvestri M, Gerardin S, Paccagnella A. Degradation induced by X-ray irradiation and channel hot carrier stresses in 130-nm NMOSFETs with enclosed layout[J]. IEEE Trans Nucl Sci, 2008, 55(6): 3216. doi: 10.1109/TNS.2008.2006747

[4]

Ker M D, Wu C Y, Wu T S. Area-efficient layout design for CMOS output transistors[J]. IEEE Trans Electron Devices, 1997, 44(4): 635. doi: 10.1109/16.563369

[5]

Champion C L, Rue G S L. Accurate SPICE models for CMOS analog radiation-hardness-by-design[J]. IEEE Trans Nucl Sci, 2005, 52(6): 2542. doi: 10.1109/TNS.2005.860717

[6]

Chen L, Gingrich D M. Study of n-channel MOSFETs with an enclosed-gate layout in a 0.18μm CMOS technology[J]. IEEE Trans Nucl Sci, 2005, 52(4): 861. doi: 10.1109/TNS.2005.852652

[7]

Jiao C, Yu Z. A robust novel technique for SPICE simulation of ESD snapback characteristic[J]. Proceedings of the 8th International Conference on Solid-State Integrated Circuit Technology, 2006: 1367.

[8]

Vassilev V, Lorenzini M, Groeseneken G. MOSFET ESD breakdown modeling and parameter extraction in advanced CMOS technologies[J]. IEEE Trans Electron Devices, 2006, 53(9): 2108. doi: 10.1109/TED.2006.880367

[9]

Li J, Joshi S, Rosenbaum E. A verilog-a compact model for ESD protection NMOSTs[J]. Proceedings of Custom Integrated Circuits Conference, 2003: 253.

[10]

Gao X, Liou J, Bernier J. Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2002, 21(12): 1497. doi: 10.1109/TCAD.2002.804379

[11]

Zhou Y Z, Connerney D, Carroll R. Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models[J]. Proceedings of the 6th International Symposium on Quality Electronic Design, San Jose, 2005: 476.

[12]

Giraldo A, Paccagnella A, Minzoni A. Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout[J]. Solid-State Electron, 2000, 44: 981. doi: 10.1016/S0038-1101(00)00010-1

[13]

Liu W D, Jin X D, Chen J, et al. BSIM3v3. 2. 2 MOSFET model users' manual. Department of Electrical Engineering and Computer Sciences University of California, Berkeley, 1999

[14]

Van der Toorn R, Paasschens J C J, Kloosterman W J. The Mextram bipolar transistor model, level 504. 10. 1. Users' Manual, Koninklijke Philips Electronics N. V. , Amsterdam, Netherlands, 2000/2004

[15]

Chen S H, Ker M D, Hung H P. Active ESD protection design for interface circuits between separated power domains against cross-power-domain ESD stresses[J]. IEEE Trans Device Mater Reliab, 2008, 8(3): 549. doi: 10.1109/TDMR.2008.2002492

[16]

Meng K H, Rosenbaum E. Verification of snapback model by transient I-V measurement for circuit simulation of ESD response[J]. IEEE Trans Device Mater Reliab, 2013, 13(2): 371. doi: 10.1109/TDMR.2013.2258672

[17]

Amerasekera A, Ramaswamy S, Chang M. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations[J]. Proceedings of the 34th Annual IEEE International Reliability Physics Symposium, Dallas, 1996: 318.

[1]

Jin Xiaoshi, Liu Xi, Wu Meile, Chuai Rongyan, Jung-Hee Lee, Jong-Ho Lee. Modeling of subthreshold characteristics for undoped and doped deep nanoscale short channel double-gate MOSFETs. J. Semicond., 2012, 33(12): 124003. doi: 10.1088/1674-4926/33/12/124003

[2]

S. Poorvasha, B. Lakshmi. Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement. J. Semicond., 2018, 39(5): 054001. doi: 10.1088/1674-4926/39/5/054001

[3]

Liu Tong, Zhu Dazhong. Relative Sensitivity of Sector Split-Drain Magnetic Field-Effect Transistor Based on Geometrical Correction Factor of Sector Hall Plate. J. Semicond., 2006, 27(12): 2155.

[4]

Nacereddine Lakhdar, Brahim Lakehal. Effect of gate engineering in submicron GaAs MESFET for microwave frequency applications. J. Semicond., 2016, 37(4): 044002. doi: 10.1088/1674-4926/37/4/044002

[5]

Ge Binjie, Wang Xin'an, Zhang Xing, Feng Xiaoxing, Wang Qingqin. Sigma–delta modulator modeling analysis and design. J. Semicond., 2010, 31(9): 095003. doi: 10.1088/1674-4926/31/9/095003

[6]

Liu Jun, Sun Lingling, Xu Xiaojun. RF-CMOS Modeling:RF-MOSFET Modeling for Low Power Applications. J. Semicond., 2007, 28(1): 131.

[7]

Lu Jing, Wang Yan, Ma Long, Yu Zhiping. A New Small-Signal Modeling and Extraction Method in AlGaN/GaN HEMTs. J. Semicond., 2007, 28(4): 567.

[8]

Jiangfeng Du, Peng Xu, Kang Wang, Chenggong Yin, Yang Liu, Zhihong Feng, Shaobo Dun, Qi Yu. Small signal modeling of AlGaN/GaN HEMTs with consideration of CPW capacitances. J. Semicond., 2015, 36(3): 034009. doi: 10.1088/1674-4926/36/3/034009

[9]

Wang Yongguang, Zhao Yongwu. Modeling the Effects of Adhesion Force on the Molecular-Scale Removal Mechanism in the Chemical Mechanical Polishing of Wafer. J. Semicond., 2007, 28(12): 2018.

[10]

Liu Jun, Sun Lingling, Xu Xiaojun. RF-CMOS Modeling:Parasitic Analysis for MOST On-Wafer Test Structure. J. Semicond., 2007, 28(2): 246.

[11]

Xia Jun, Wang Zhigong, Wu Xiushan, Li Wei. Analysis and Modeling of Broadband CMOS Monolithic Balun up to Millimeter-Wave Frequencies. J. Semicond., 2008, 29(3): 467.

[12]

Le Yu, Yingkui Zheng, Sheng Zhang, Lei Pang, Ke Wei, Xiaohua Ma. Small-signal model parameter extraction for AlGaN/GaN HEMT. J. Semicond., 2016, 37(3): 034003. doi: 10.1088/1674-4926/37/3/034003

[13]

Muhammad Nawaz, Ashfaq Ahmad. Influence of absorber doping in a-SiC:H/a-Si:H/a-SiGe:H solar cells. J. Semicond., 2012, 33(4): 042001. doi: 10.1088/1674-4926/33/4/042001

[14]

Zhiqun Cheng, Minshi Jia, Ya Luan, Xinxiang Lian. Solid-state wideband GaN HEMT power amplifier with a novel negative feedback structure. J. Semicond., 2014, 35(12): 125005. doi: 10.1088/1674-4926/35/12/125005

[15]

Liu Dan, Chen Xiaojuan, Liu Xinyu, Wu Dexin. A 22-Element Small-Signal Model of GaN HEMT Devices. J. Semicond., 2007, 28(9): 1438.

[16]

G.I. Zebrev, M.G. Drosdetsky, A.M. Galimov. Non-equilibrium carrier capture, recombination and annealing in thick insulators and their impact on radiation hardness. J. Semicond., 2016, 37(11): 115001. doi: 10.1088/1674-4926/37/11/115001

[17]

Ning Zhu, Wei Li, Ning Li, Junyan Ren. A 20-25.5 GHz VCO using a new variable inductor for K band application. J. Semicond., 2013, 34(12): 125005. doi: 10.1088/1674-4926/34/12/125005

[18]

Jeetendra Singh, Balwinder Raj. Comparative analysis of memristor models and memories design. J. Semicond., 2018, 39(7): 074006. doi: 10.1088/1674-4926/39/7/074006

[19]

Liu Jun, Sun Lingling. III-V Compound HBT Modeling. J. Semicond., 2005, 26(11): 2175.

[20]

Wang Qiang, Chen Lan, Li Zhigang, Ruan Wenbiao. An electroplating topography model based on layout-dependent variation of copper deposition rate. J. Semicond., 2011, 32(10): 105012. doi: 10.1088/1674-4926/32/10/105012

Search

Advanced Search >>

GET CITATION

J Zhang, H G Yang, J B Sun, L Yu, Y F Wei. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method[J]. J. Semicond., 2014, 35(8): 085001. doi: 10.1088/1674-4926/35/8/085001.

Export: BibTex EndNote

Article Metrics

Article views: 554 Times PDF downloads: 6 Times Cited by: 0 Times

History

Manuscript received: 14 January 2014 Manuscript revised: 27 January 2014 Online: Published: 01 August 2014

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误