J. Semicond. > Volume 37 > Issue 2 > Article Number: 024004

A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

Chaowen Liu , Jingping Xu , , Lu Liu , Hanhan Lu and Yuan Huang

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Abstract: A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored.

Key words: GaAs MOSFETthreshold voltagestack high-k gate dielectricquantum effect

Abstract: A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored.

Key words: GaAs MOSFETthreshold voltagestack high-k gate dielectricquantum effect



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[1]

Passlack M, Hong M, Mannaerts J. Low Dit thermodynamically stable Ga2O3-GaAs interfaces: fabrication, characterization, and modeling[J]. IEEE Trans Electron Devices, 1997, 44(2): 214.

[2]

Wilk G D, Wallace R M, Anthony J M. High-k gate dielectrics: current status and materials properties considerations[J]. J Appl Phys, 2001, 89(10): 5243.

[3]

Dalapati G K, Sridhara A, Wong A S W. HfOxNy gate dielectric on p-GaAs[J]. Appl Phys Lett, 2009, 94(7): 073502.

[4]

Das P S, Biswas A. Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates[J]. Microelectron Reliab, 2012, 52(1): 112.

[5]

Wang X W, Dong L, Zhang J Y. Heteroepitaxy of La2O3 and La(2-x)Y(x)O3 on GaAs(111)A by atomic layer deposition: achieving low interface trap density[J]. Nano Lett, 2013, 13(2): 594.

[6]

Gordon R G, Dong L, Wang X W. GaAs Enhancement-mode NMOSFETs enabled by atomic layer epitaxial/La1,8Y0.2O3 as dielectric[J]. IEEE Electron Device Lett, 2013, 34(4): 487.

[7]

Liu X Y, Kang J F, Sun L. Threshold voltage model for MOSFETs with high-k gate dielectrics[J]. IEEE Electron Device Lett, 2002, 23(5): 270.

[8]

Ji F, Xu J P, Lai P T. 2D Threshold-voltage model for high-k gate-dielectric MOSFETs[J]. Chinese Journal of Semiconductors, 2006, 27(10): 1725.

[9]

Ma Y, Li Z, Liu L. Effective density-of-states approach to QM correction in MOS structures[J]. Solid-state Electron, 2000, 44(3): 401.

[10]

Liu Z H, Hu C. Threshold voltage model for deep-submicrometer MOSFET's[J]. IEEE Trans Electron Devices, 1993, 40(1): 86.

[11]

Chen J J. Electronic characteristic simulation and preparation process analysis of Ge-MOS with high-k gate dielectric:[J]. Huazhong University of Science & Technology, 2009.

[12]

Ma Y, Liu L, Tian L. Analytical charge-control and I-V model for submicrometer and deep-submicrometer MOSFETs fully comprising quantum mechanical effects[J]. IEEE Trans Comput-Aided Design Integr Circuits Syst, 2001, 20(4): 495.

[13]

Dai Y H, Chen J N. An analytical model of MOSFET threshold voltage with considering the quantum effects[J]. Acta Phys Sin, 2005, 54(2): 897.

[14]

Li Y P, Xu J P, Chen W B. 2-D threshold voltage model for short-channel MOSFET with quantum-mechanical effects[J]. Acta Phys Sin, 2006, 55(7): 3670.

[15]

Ye P D, Wilk G D, Kwo J. GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition[J]. IEEE Electron Device Lett, 2003, 24(4): 209.

[16]

Yeap G C F, Krishnan S, Lin M R. Fringing-induced barrier lowering (FIBL) in sub-100-nm MOSFETs with high-k gate dielectrics[J]. Electron Lett, 1998, 34(11): 1150.

[17]

Yang T, Xuan Y, Zemlyanov D. Interface studies of GaAs metal-oxide-semiconductor structures using atomic-layer-deposited HfO2/Al2O3 nanolaminate gate dielectric[J]. Appl Phys Lett, 2007, 91(14): 142122.

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C W Liu, J P Xu, L Liu, H H Lu, Y Huang. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric[J]. J. Semicond., 2016, 37(2): 024004. doi: 10.1088/1674-4926/37/2/024004.

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Manuscript received: 26 June 2015 Manuscript revised: Online: Published: 01 February 2016

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