J. Semicond. > Volume 37 > Issue 5 > Article Number: 054002

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications

Pranav Kumar Asthana 1, , Yogesh Goswami 1, and Bahniman Ghosh 1, 2,

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Abstract: We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in IOFF of ~ 9 × 10-16A/μm, ION of ~20 μA/μm, ION/IOFF of ~2 × 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.

Key words: band-to-band tunneling (BTBT)tunnel field effect transistor (TFET)junctionless tunnel field effect transistor (JLTFET)ION/IOFF ratiolow power

Abstract: We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in IOFF of ~ 9 × 10-16A/μm, ION of ~20 μA/μm, ION/IOFF of ~2 × 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.

Key words: band-to-band tunneling (BTBT)tunnel field effect transistor (TFET)junctionless tunnel field effect transistor (JLTFET)ION/IOFF ratiolow power



References:

[1]

Lilienfeld J E. Method and apparatus for controlling electric current[J]. Patent 1745175, 1930.

[2]

Colinge J P, Lee C W, Afzalian A. Nanowire transistors without junctions[J]. Nature Nanotechnol, 2010, 5: 225.

[3]

Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric[J]. IEEE Trans Electron Devices, 2007, 54(7): 1725.

[4]

Ionescu A M, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches[J]. Nature, 2011, 479: 329.

[5]

Kazazis D, Jannaty P, Zaslavsky A. Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator[J]. Appl Phys Lett, 2009, 94: 263508.

[6]

Toh E H, Wang G H, Lo G Q. Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering[J]. Appl Phys Lett, 2007, 90: 023505.

[7]

Ganapathi K, Yoon Y, Salahuddin S. Analysis of InAs vertical and lateral band-to-band tunneling transistors: leveraging vertical tunneling for improved performance[J]. Appl Phys Lett, 2010, 97: 033504.

[8]

Wang C, Chou S Y. Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching[J]. J Vac Sci Technol B, 2009, 27: 2790.

[9]

Ghosh B, Akram M W. Junctionless tunnel field effect transistor[J]. IEEE Electron Device Lett, 2013, 34: 584.

[10]

Ghosh B, Bal P, Mondal P. A junctionless tunnel field effect transistor with low subthreshold slope[J]. J Comput Electron, 2013, 12: 428.

[11]

Goswami Y, Ghosh B, Asthana P K. Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III-V semiconductor[J]. RSC Advances, 2014, 4: 10761.

[12]

Goswami Y, Tripathi B M M, Asthana P. Junctionless tunnel field effect transistor with enhanced performance using III-V semiconductor[J]. Journal of Low Power Electronics, 2013, 9: 496.

[13]

Ghosh B, Bal P, Mondal P. A junctionless tunnel field effect transistor with low subthreshold slope[J]. J Comput Electron, 2013, 12: 428.

[14]

Lee C W, Afzalian A, Akhavan N D. Junctionless multigate field-effect transistor[J]. Appl Phys Lett, 2009, 94: 053511.

[15]

Kumar M J, Janardhanan S. Doping-less tunnel field effect transistor: design and investigation[J]. IEEE Trans Electron Devices, 2013, 60: 3285.

[16]

Takei K, Kapadia R, Fang H. High quality interfaces of InAs-on-insulator field-effect transistors with ZrO2 gate dielectrics[J]. Appl Phys Lett, 2013, 102: 153513.

[17]

Takei K, Chuang S, Fang H. Benchmarking the performance of ultrathin body InAs-on-insulator transistors as a function of body thickness[J]. Appl Phys Lett, 2011, 99: 103507.

[18]

Ford A C, Yeung C W, Chuang S. Ultrathin body InAs tunneling field-effect transistors on Si substrates[J]. Appl Phys Lett, 2011, 98: 113105.

[19]

Hiramoto T, Kumar A, Mizutani T. Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs[J]. IEEE Custom Integrated Circuits Conference (CICC), 2011: 1.

[20]

Hiramoto T, Mizutani T, Umar A. Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs[J]. IEEE International SOI Conference (SOI), 2010.

[21]

Ye P D, Wilk G D, Kwo J. GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition[J]. IEEE Electron Device Lett, 2003, 24: 209.

[22]

Hinkle C L, Sonnet A M, Vogel E M. GaAs interfacial self-cleaning by atomic layer deposition[J]. Appl Phys Lett, 2008, 92: 071901.

[23]

Xuan Y, Lin H C, Ye P D. Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric[J]. Appl Phys Lett, 2006, 88: 263518.

[24]

ATLAS Device Simulation Software, Silvaco Int. Santa Clara, CA, USA[J]. , 2012.

[25]

Schenk, A. A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon[J]. Solid-State Electron, 1992, 35(11): 1585.

[26]

Kumar M J, Siva M. The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs[J]. IEEE Trans Electron Devices, 2008, 55: 1554.

[27]

Hu C C. Modern semiconductor devices for integrated circuits[J]. , 2010: 279.

[1]

Lilienfeld J E. Method and apparatus for controlling electric current[J]. Patent 1745175, 1930.

[2]

Colinge J P, Lee C W, Afzalian A. Nanowire transistors without junctions[J]. Nature Nanotechnol, 2010, 5: 225.

[3]

Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric[J]. IEEE Trans Electron Devices, 2007, 54(7): 1725.

[4]

Ionescu A M, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches[J]. Nature, 2011, 479: 329.

[5]

Kazazis D, Jannaty P, Zaslavsky A. Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator[J]. Appl Phys Lett, 2009, 94: 263508.

[6]

Toh E H, Wang G H, Lo G Q. Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering[J]. Appl Phys Lett, 2007, 90: 023505.

[7]

Ganapathi K, Yoon Y, Salahuddin S. Analysis of InAs vertical and lateral band-to-band tunneling transistors: leveraging vertical tunneling for improved performance[J]. Appl Phys Lett, 2010, 97: 033504.

[8]

Wang C, Chou S Y. Self-aligned fabrication of 10 nm wide asymmetric trenches for Si/SiGe heterojunction tunneling field effect transistors using nanoimprint lithography, shadow evaporation, and etching[J]. J Vac Sci Technol B, 2009, 27: 2790.

[9]

Ghosh B, Akram M W. Junctionless tunnel field effect transistor[J]. IEEE Electron Device Lett, 2013, 34: 584.

[10]

Ghosh B, Bal P, Mondal P. A junctionless tunnel field effect transistor with low subthreshold slope[J]. J Comput Electron, 2013, 12: 428.

[11]

Goswami Y, Ghosh B, Asthana P K. Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III-V semiconductor[J]. RSC Advances, 2014, 4: 10761.

[12]

Goswami Y, Tripathi B M M, Asthana P. Junctionless tunnel field effect transistor with enhanced performance using III-V semiconductor[J]. Journal of Low Power Electronics, 2013, 9: 496.

[13]

Ghosh B, Bal P, Mondal P. A junctionless tunnel field effect transistor with low subthreshold slope[J]. J Comput Electron, 2013, 12: 428.

[14]

Lee C W, Afzalian A, Akhavan N D. Junctionless multigate field-effect transistor[J]. Appl Phys Lett, 2009, 94: 053511.

[15]

Kumar M J, Janardhanan S. Doping-less tunnel field effect transistor: design and investigation[J]. IEEE Trans Electron Devices, 2013, 60: 3285.

[16]

Takei K, Kapadia R, Fang H. High quality interfaces of InAs-on-insulator field-effect transistors with ZrO2 gate dielectrics[J]. Appl Phys Lett, 2013, 102: 153513.

[17]

Takei K, Chuang S, Fang H. Benchmarking the performance of ultrathin body InAs-on-insulator transistors as a function of body thickness[J]. Appl Phys Lett, 2011, 99: 103507.

[18]

Ford A C, Yeung C W, Chuang S. Ultrathin body InAs tunneling field-effect transistors on Si substrates[J]. Appl Phys Lett, 2011, 98: 113105.

[19]

Hiramoto T, Kumar A, Mizutani T. Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs[J]. IEEE Custom Integrated Circuits Conference (CICC), 2011: 1.

[20]

Hiramoto T, Mizutani T, Umar A. Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs[J]. IEEE International SOI Conference (SOI), 2010.

[21]

Ye P D, Wilk G D, Kwo J. GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition[J]. IEEE Electron Device Lett, 2003, 24: 209.

[22]

Hinkle C L, Sonnet A M, Vogel E M. GaAs interfacial self-cleaning by atomic layer deposition[J]. Appl Phys Lett, 2008, 92: 071901.

[23]

Xuan Y, Lin H C, Ye P D. Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric[J]. Appl Phys Lett, 2006, 88: 263518.

[24]

ATLAS Device Simulation Software, Silvaco Int. Santa Clara, CA, USA[J]. , 2012.

[25]

Schenk, A. A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon[J]. Solid-State Electron, 1992, 35(11): 1585.

[26]

Kumar M J, Siva M. The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs[J]. IEEE Trans Electron Devices, 2008, 55: 1554.

[27]

Hu C C. Modern semiconductor devices for integrated circuits[J]. , 2010: 279.

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P K Asthana, Y Goswami, B Ghosh. A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications[J]. J. Semicond., 2016, 37(5): 054002. doi: 10.1088/1674-4926/37/5/054002.

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Manuscript received: 06 September 2015 Manuscript revised: Online: Published: 01 May 2016

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