Fig. 1.
Architecture of DLX RISC processor.
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G. Prasad Acharya, M. Asha Rani. Berger code based concurrent online self-testing of embedded processors[J]. Journal of Semiconductors, 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001
G P Acharya, M A Rani, Berger code based concurrent online self-testing of embedded processors[J]. J. Semicond., 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001.
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Berger code based concurrent online self-testing of embedded processors
doi: 10.1088/1674-4926/39/11/115001
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Abstract
We propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable architecture is proposed and integrated in 32-bit DLX reduced instruction set computer (RISC) processor on a single silicon chip. The proposed concurrent test methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults.-
Keywords:
- single event upset,
- Berger code,
- DLX RISC,
- online testing
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References
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