SEMICONDUCTOR INTEGRATED CIRCUITS

An advanced SEU tolerant latch based on error detection

Hui Xu1, 3, Jianwei Zhu2, , Xiaoping Lu2 and Jingzhao Li2

+ Author Affiliations

 Corresponding author: Jianwei Zhu, E-mail address: zhujw68@163.com

PDF

Turn off MathJax

Abstract: This paper proposes a latch that can mitigate SEUs via an error detection circuit. The error detection circuit is hardened by a C-element and a stacked PMOS. In the hold state, a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit. The error detection circuit can detect the upset node in the latch and the fault output will be corrected. The upset node in the error detection circuit can be corrected by the C-element. The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations. The proposed latch consumes about 77.5% less energy and 33.1% less propagation delay than the triple modular redundancy (TMR) latch. Simulation results demonstrate that the proposed latch can mitigate SEU effectively.

Key words: single event upset (SEU)latcherror detectionstacked



[1]
Karnik T, Hazucha P. Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans Depend Secure Comput, 2004, 1(2): 128 doi: 10.1109/TDSC.2004.14
[2]
Schrimpf R D, Warren K M, Weller R A, et al. Reliability and radiation effects in IC technologies. IEEE International Reliability Physics Symposium, 2008: 97
[3]
Ueno H, Namba K. Construction of a soft error (SEU) hardened latch with high critical charge. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016: 27
[4]
The international technology roadmap for semiconductors. [Online]. Available: http://www.itrs.net/Links/2001ITRS/ Design.pdf
[5]
Wang H B, Li Y Q, Chen L, et al. An SEU-tolerant DICE latch design with feedback transistors. IEEE Trans Nucl Sci, 2015, 62(2): 548 doi: 10.1109/TNS.2015.2399019
[6]
Nicolaidis M. Design for soft error mitigation. IEEE Trans Device Mater Reliab, 2005, 5: 405 doi: 10.1109/TDMR.2005.855790
[7]
Pontes J, Calazans N, Vivet P. Adding temporal redundancy to delay insensitive codes to mitigate single event effects. IEEE International Symposium on Asynchronous Circuits and Systems, 2012: 142
[8]
Carmichael C, Fuller E, Blain P, et al. SEU mitigation techniques for Virtex FPGAs in space applications. Proc Military and Aerospace Programmable Logic Devices Int Conf, 1999: C2
[9]
Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci, 1996, 43(6): 2874 doi: 10.1109/23.556880
[10]
Huang Z F, Liang H G. A novel radiation hardened by design latch. J Semicond, 2009, 30(3): 035007 doi: 10.1088/1674-4926/30/3/035007
[11]
Makihara A, Yamaguchi T, Asai H, et al. Optimization for SEU/SET immunity on 0.15 μm fully depleted CMOS/SOI digital logic devices. IEEE Trans Nucl Sci, 2006, 53(6): 3422 doi: 10.1109/TNS.2006.885166
[12]
Rodbell K P, Heidel D F, Pellish J A, et al. 32 and 45 nm radiation-hardened-by-design (RHBD) SOI latches. IEEE Trans Nucl Sci, 2011, 58(6): 2702 doi: 10.1109/TNS.2011.2171715
[13]
Kauppila J S, Loveless T D, Quinn R C, et al. Utilizing device stacking for area efficient hardened SOI flip-flop designs. IEEE International Reliability Physics Symposium, 2014: SE.4.1
[14]
Wang H B, Chen L, Liu R, et al. An area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology. IEEE Trans Nucl Sci, 2016, 63(6): 3003 doi: 10.1109/TNS.2016.2627003
[15]
Zhao W, Cao Y. New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans Electron Devices, 2006, 53(11): 2816 doi: 10.1109/TED.2006.884077
[16]
She X, Li N, Tong J. SEU tolerant latch based on error detection. IEEE Trans Nucl Sci, 2012, 59(1): 211 doi: 10.1109/TNS.2011.2178265
[17]
Oliveira R, Jagirdar A, Chakraborty T J. A TMR scheme for SEU mitigation in scan flip-flops. Proc 8th Int Symp Qual Electron Des, 2007: 905
[18]
Iturbe X, Azkarate M, Martinez I, et al. A novel SEU, MBU and SHE handling strategy for xilinx virtex-4 FPGAs. Proc Int Conf Field Program Logic Appl, 2009: 569
[19]
Tanoue S, Ishida T, Ichinomiya Y, et al. A novel states recovery technique for the TMR softcore processor. Proc Int Conf Field Program Logic Appl, 2009: 543
[20]
Stroud C E. Reliability of majority voting based VLSI fault-tolerant circuits. IEEE Trans VLSI Syst, 1994, 2: 516 doi: 10.1109/92.335020
[21]
Huang Z. A high performance SEU-tolerant latch for nanoscale CMOS technology. J Electron Test, 2015, 31(4): 1
[22]
Rajaei R, Tabandeh M, Rashidian B. Single event upset immune latch circuit design using C-element. IEEE 9th International Conference on ASIC (ASICON), 2011: 252
Fig. 1.  The standard static latch.

Fig. 2.  (a) C-element. (b) C-element truth table.

Fig. 3.  The proposed SEU tolerant latch.

Fig. 4.  (Color online) The experimental results when an SEU was injected at node A, node B, node E0, node E1.

Fig. 5.  (Color online) (a) Power dissipation. (b) Propagation delay.

[1]
Karnik T, Hazucha P. Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans Depend Secure Comput, 2004, 1(2): 128 doi: 10.1109/TDSC.2004.14
[2]
Schrimpf R D, Warren K M, Weller R A, et al. Reliability and radiation effects in IC technologies. IEEE International Reliability Physics Symposium, 2008: 97
[3]
Ueno H, Namba K. Construction of a soft error (SEU) hardened latch with high critical charge. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016: 27
[4]
The international technology roadmap for semiconductors. [Online]. Available: http://www.itrs.net/Links/2001ITRS/ Design.pdf
[5]
Wang H B, Li Y Q, Chen L, et al. An SEU-tolerant DICE latch design with feedback transistors. IEEE Trans Nucl Sci, 2015, 62(2): 548 doi: 10.1109/TNS.2015.2399019
[6]
Nicolaidis M. Design for soft error mitigation. IEEE Trans Device Mater Reliab, 2005, 5: 405 doi: 10.1109/TDMR.2005.855790
[7]
Pontes J, Calazans N, Vivet P. Adding temporal redundancy to delay insensitive codes to mitigate single event effects. IEEE International Symposium on Asynchronous Circuits and Systems, 2012: 142
[8]
Carmichael C, Fuller E, Blain P, et al. SEU mitigation techniques for Virtex FPGAs in space applications. Proc Military and Aerospace Programmable Logic Devices Int Conf, 1999: C2
[9]
Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci, 1996, 43(6): 2874 doi: 10.1109/23.556880
[10]
Huang Z F, Liang H G. A novel radiation hardened by design latch. J Semicond, 2009, 30(3): 035007 doi: 10.1088/1674-4926/30/3/035007
[11]
Makihara A, Yamaguchi T, Asai H, et al. Optimization for SEU/SET immunity on 0.15 μm fully depleted CMOS/SOI digital logic devices. IEEE Trans Nucl Sci, 2006, 53(6): 3422 doi: 10.1109/TNS.2006.885166
[12]
Rodbell K P, Heidel D F, Pellish J A, et al. 32 and 45 nm radiation-hardened-by-design (RHBD) SOI latches. IEEE Trans Nucl Sci, 2011, 58(6): 2702 doi: 10.1109/TNS.2011.2171715
[13]
Kauppila J S, Loveless T D, Quinn R C, et al. Utilizing device stacking for area efficient hardened SOI flip-flop designs. IEEE International Reliability Physics Symposium, 2014: SE.4.1
[14]
Wang H B, Chen L, Liu R, et al. An area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology. IEEE Trans Nucl Sci, 2016, 63(6): 3003 doi: 10.1109/TNS.2016.2627003
[15]
Zhao W, Cao Y. New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans Electron Devices, 2006, 53(11): 2816 doi: 10.1109/TED.2006.884077
[16]
She X, Li N, Tong J. SEU tolerant latch based on error detection. IEEE Trans Nucl Sci, 2012, 59(1): 211 doi: 10.1109/TNS.2011.2178265
[17]
Oliveira R, Jagirdar A, Chakraborty T J. A TMR scheme for SEU mitigation in scan flip-flops. Proc 8th Int Symp Qual Electron Des, 2007: 905
[18]
Iturbe X, Azkarate M, Martinez I, et al. A novel SEU, MBU and SHE handling strategy for xilinx virtex-4 FPGAs. Proc Int Conf Field Program Logic Appl, 2009: 569
[19]
Tanoue S, Ishida T, Ichinomiya Y, et al. A novel states recovery technique for the TMR softcore processor. Proc Int Conf Field Program Logic Appl, 2009: 543
[20]
Stroud C E. Reliability of majority voting based VLSI fault-tolerant circuits. IEEE Trans VLSI Syst, 1994, 2: 516 doi: 10.1109/92.335020
[21]
Huang Z. A high performance SEU-tolerant latch for nanoscale CMOS technology. J Electron Test, 2015, 31(4): 1
[22]
Rajaei R, Tabandeh M, Rashidian B. Single event upset immune latch circuit design using C-element. IEEE 9th International Conference on ASIC (ASICON), 2011: 252
  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3914 Times PDF downloads: 65 Times Cited by: 0 Times

    History

    Received: 14 August 2017 Revised: 11 December 2017 Online: Accepted Manuscript: 13 January 2018Uncorrected proof: 24 January 2018Published: 01 May 2018

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Hui Xu, Jianwei Zhu, Xiaoping Lu, Jingzhao Li. An advanced SEU tolerant latch based on error detection[J]. Journal of Semiconductors, 2018, 39(5): 055003. doi: 10.1088/1674-4926/39/5/055003 H Xu, J W Zhu, X P Lu, J Z Li. An advanced SEU tolerant latch based on error detection[J]. J. Semicond., 2018, 39(5): 055003. doi: 10.1088/1674-4926/39/5/055003.Export: BibTex EndNote
      Citation:
      Hui Xu, Jianwei Zhu, Xiaoping Lu, Jingzhao Li. An advanced SEU tolerant latch based on error detection[J]. Journal of Semiconductors, 2018, 39(5): 055003. doi: 10.1088/1674-4926/39/5/055003

      H Xu, J W Zhu, X P Lu, J Z Li. An advanced SEU tolerant latch based on error detection[J]. J. Semicond., 2018, 39(5): 055003. doi: 10.1088/1674-4926/39/5/055003.
      Export: BibTex EndNote

      An advanced SEU tolerant latch based on error detection

      doi: 10.1088/1674-4926/39/5/055003
      Funds:

      Project supported by the National Natural Science Foundation of China (Nos. 61404001, 61306046), the Anhui Province University Natural Science Research Major Project (No. KJ2014ZD12), the Huainan Science and Technology Program (No. 2013A4011), and the National Natural Science Foundation of China (No. 61371025).

      More Information
      • Corresponding author: E-mail address: zhujw68@163.com
      • Received Date: 2017-08-14
      • Revised Date: 2017-12-11
      • Published Date: 2018-05-01

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return