J. Semicond. > Volume 40 > Issue 1 > Article Number: 012803

Source-field-plated Ga2O3 MOSFET with a breakdown voltage of 550 V

Yuanjie Lü , Xubo Song , Zezhao He , Yuangang Wang , Xin Tan , Shixiong Liang , Cui Wei , Xingye Zhou , and Zhihong Feng ,

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Abstract: Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga2O3 film, which was grown by metal organic chemical vapor deposition (MOCVD) on an Fe-doped semi-insulating (010) Ga2O3 substrate. The structure consisted of a 400 nm unintentionally doped (UID) Ga2O3 buffer layer and an 80 nm Si-doped channel layer. A high k HfO2 gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at Vgs of 3 V. The off-state current was as low as 7.1 × 10−11 A/mm, and the drain current ION/IOFF ratio reached 109. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.

Key words: Ga2O3MOSFETbreakdown voltagefiled plate

Abstract: Ga2O3 metal–oxide–semiconductor field-effect transistors (MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga2O3 film, which was grown by metal organic chemical vapor deposition (MOCVD) on an Fe-doped semi-insulating (010) Ga2O3 substrate. The structure consisted of a 400 nm unintentionally doped (UID) Ga2O3 buffer layer and an 80 nm Si-doped channel layer. A high k HfO2 gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at Vgs of 3 V. The off-state current was as low as 7.1 × 10−11 A/mm, and the drain current ION/IOFF ratio reached 109. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.

Key words: Ga2O3MOSFETbreakdown voltagefiled plate



References:

[1]

Zhang H Z, Wang L J, Xia C T, et al. Research progress of wide-gap semiconductor β-Ga2O3 single crystal. J Synth Cryst, 2015, 44: 2943

[2]

Gogova D, Wagner G, Balndini M, et al. Structural properties of Si-doped β-Ga2O3 layers grown by MOVPE. J Cryst Growth, 2014, 401: 665

[3]

Higashiwaki M, Sasali K, Kuramata T, et al. Depletion-mode Ga2O3 metal–oxide–semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics. Appl Phys Lett, 2013, 103: 123511

[4]

Wong M H, Sasaki K, Kuramata A, et al. Field-plated Ga2O3 MOSFET with a breakdown voltage of over 750V. IEEE Electron Device Lett, 2016, 37: 212

[5]

Zhou H, Maize K, Qiu G, et al. β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect. Appl Phys Lett, 2017, 111: 092102

[6]

Han T T, Lv Y J, Liu P, et al. Research and Fabrication of Ga2O3 MOSFET device with HfO2 gate dielectric. Semicond Technol, 2018, 43: 177

[7]

Lv Y J, Mo J H, Song X B, et al. Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs. Superlattices Microstruct, 2018, 117:132

[1]

Zhang H Z, Wang L J, Xia C T, et al. Research progress of wide-gap semiconductor β-Ga2O3 single crystal. J Synth Cryst, 2015, 44: 2943

[2]

Gogova D, Wagner G, Balndini M, et al. Structural properties of Si-doped β-Ga2O3 layers grown by MOVPE. J Cryst Growth, 2014, 401: 665

[3]

Higashiwaki M, Sasali K, Kuramata T, et al. Depletion-mode Ga2O3 metal–oxide–semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics. Appl Phys Lett, 2013, 103: 123511

[4]

Wong M H, Sasaki K, Kuramata A, et al. Field-plated Ga2O3 MOSFET with a breakdown voltage of over 750V. IEEE Electron Device Lett, 2016, 37: 212

[5]

Zhou H, Maize K, Qiu G, et al. β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect. Appl Phys Lett, 2017, 111: 092102

[6]

Han T T, Lv Y J, Liu P, et al. Research and Fabrication of Ga2O3 MOSFET device with HfO2 gate dielectric. Semicond Technol, 2018, 43: 177

[7]

Lv Y J, Mo J H, Song X B, et al. Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs. Superlattices Microstruct, 2018, 117:132

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Y J Lü, X B Song, Z Z He, Y G Wang, X Tan, S X Liang, C Wei, X Y Zhou, Z H Feng, Source-field-plated Ga2O3 MOSFET with a breakdown voltage of 550 V[J]. J. Semicond., 2019, 40(1): 012803. doi: 10.1088/1674-4926/40/1/012803.

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History

Manuscript received: 07 June 2018 Manuscript revised: 05 July 2018 Online: Uncorrected proof: 20 November 2018 Published: 07 January 2019

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