J. Semicond. > 2018, Volume 39 > Issue 9 > 094011, doi: 10.1088/1674-4926/39/9/094011
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SEMICONDUCTOR DEVICES

Impact of ambient temperature on the self-heating effects in FinFETs

Longxiang Yin, Gang Du and Xiaoyan Liu

+ Author Affiliations

 Corresponding author: Xiaoyan Liu, Email: xyliu@ime.pku.edu.cn

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Abstract: We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect (SHE) in 14 nm bulk nFinFETs with ambient temperature (TA) from 220 to 400 K. Based on this method, non-local heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/SiO2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) not all input power (Qinput) turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport; (ii) a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages; (iii) SHE can lead to serious degradation in the carrier transport, which will increase when TA increases; (iv) the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K; (v) device thermal resistance (Rth) increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.

Key words: self-heating effects, ambient temperature, FinFET, Monte Carlo method



[1]
Pop E. Energy dissipation and transport in nanoscale devices. Nano Res, 2010, 3(3): 147 doi: 10.1007/s12274-010-1019-z
[2]
Semenov O, Vassighi A, Sachdev M. Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits. IEEE Trans Device Mater Rel, 2006, 6(1): 17 doi: 10.1109/TDMR.2006.870340
[3]
Shapiro A, Friedman E G. Power efficient level shifter for 16nm FinFET near threshold circuits. IEEE Trans VLSI Syst, 2016, 24(2): 774 doi: 10.1109/TVLSI.2015.2409051
[4]
Makovejev S, Planes N, Haond M, et al. Self-heating in 28 nm bulk and FDSOI. Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2015: 41
[5]
Bury E, Kaczer B, Linten D, et al. Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels. IEEE International Electron Devices Meeting (IEDM), 2016: 15.6.1
[6]
Bury E, Kaczer B, Mitard J, et al. Characterization of self-heating in high-mobility Ge FinFET pMOS devices. Symposium on VLSI Technology (VLSI Technology), 2015: T60
[7]
Wahab M A, Shin S H, Alam M A. 3D modeling of spatio-temporal heat-transport in III–V gate-all-around transistors allows accurate estimation and optimization of nanowire temperature. IEEE Trans Electron Devices, 2015, 62(11): 3595 doi: 10.1109/TED.2015.2478844
[8]
Liao M H, Hsieh C P, Lee C C. Systematic investigation of self-heating effect on CMOS logic transistors from 20 to 5 nm technology nodes by experimental thermoelectric measurements and finite element modeling. IEEE Trans Electron Devices, 2017, 64(2): 646 doi: 10.1109/TED.2016.2642404
[9]
Jin M, Liu C, Kim J, et al. Hot carrier reliability characterization in consideration of self-heating in FinFET technology. IEEE International Reliability Physics Symposium (IRPS), 2016: 2A-2-1
[10]
Jiang H, Shin S H, Liu X, et al. The impact of self-heating on HCI reliability in high-performance digital circuits. IEEE Device Lett, 2017, 38(4): 430 doi: 10.1109/LED.2017.2674658
[11]
Jiang H, Shen L, Shin S H, et al. Unified self-heating effect model for advanced digital and analog technology and thermal-aware lifetime prediction methodology. Symposium on VLSI Technology (VLSI Technology), 2017: T136
[12]
Si M W, Shin S H, Conrad N J, et al. Characterization and reliability of III–V gate-all-around MOSFETs. IEEE International Reliability Physics Symposium (IRPS), 2015: 4A.1.1
[13]
Jiang H, Liu X Y, Xu N, et al. Investigation of self-heating effect on hot carrier degradation in multiple-fin SOI FinFETs. IEEE Electron Device Lett, 2015, 36(12): 1258 doi: 10.1109/LED.2015.2487045
[14]
Vasileska D. Modeling self-heating in nanoscale devices. IEEE International Conference on Nanotechnology (IEEE-NANO), 2015: 200
[15]
Kamakura Y, Adisusilo I N, Kukita K, et al. Coupled Monte Carlo simulation of transient electron-phonon transport in small FETs. IEEE International Electron Devices Meeting (IEDM), 2014: 176
[16]
BSIM CMG, http://bsim.berkeley.edu/models/bsimcmg/, BSIM Group, 2015
[17]
Pierret R F. Semiconductor device fundamentals. Reading: Addison-Wesley, 1996
[18]
Fischetti M V, Laux S E. Monte Carlo analysis of electron transport in small semiconductor devices including band-structure and space-charge effects. Phys Rev B, 1988, 38(14): 9721 doi: 10.1103/PhysRevB.38.9721
[19]
Mohamed M, Aksamija Z, Vitale W, et al. A conjoined electron and thermal transport study of thermal degradation induced during normal operation of multigate transistors. IEEE Trans Electron Devices, 2014, 61(4): 976 doi: 10.1109/TED.2014.2306422
[20]
Gonzalez B, Palankovski V, Kosina H, et al. An analytical model for the electron energy relaxation time. International Association of Science and Technology for Development (IASTED), 1999: 367
[21]
Jeon J, Jhon H S, Kang M. Investigation of electrothermal behaviors of 5 nm Bulk FinFET. IEEE Trans Electron Devices, 2017, 64(12): 5284 doi: 10.1109/TED.2017.2766214
[22]
Wang L, Brown A R, Nedjalkov M, et al. Impact of self-heating on the statistical variability in bulk and SOI FinFETs. IEEE Trans Electron Devices, 2015, 62(7): 2106 doi: 10.1109/TED.2015.2436351
[23]
https://www.altera.com/products/common/temperature/ind-temp.html, 2017
[24]
Xie B Q, Bi J S, Li B, et al. The effect of cryogenic temperature characteristics on silicon-based devices and circuits. Microelectronics, 2015, 45(6): 789 (in Chinese)
[25]
Natarajan S, Agostinelli M, Akbar S, et al. A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size. IEEE International Electron Devices Meeting (IEDM), 2014: 71
[26]
ITRS. www.itrs2.net/itrs-reports.html, ITRS Reports, 2013
[27]
Wang J C, Du G, Wei K L, et al. Three-dimensional Monte Carlo simulation of bulk fin field effect transistor. Chin Phys B, 2012, 21(11): 117308 doi: 10.1088/1674-1056/21/11/117308
[28]
Wei K L, Egley J, Liu X Y, et al. Remote charge scattering: a full Coulomb interaction approach and its impact on silicon nMOS FinFETs with HfO2 gate dielectric. Sci China Inf Sci, 2014, 57(2): 022403
[29]
Du G, Liu X Y, Han R Q. Quantum Boltzmann equation solved by Monte Carlo method for nanoscale semiconductor devices. Chin Phys, 2006, 15(1): 177 doi: 10.1088/1009-1963/15/1/028
[30]
Du G, Liu X Y, Xia Z L, et al. Monte Carlo simulation of p- and n-channel GOI MOSFETs by solving the quantum Boltzmann equation. IEEE Trans Electron Devices, 2005, 52(10): 2258 doi: 10.1109/TED.2005.856806
[31]
Jacoboni C, Reggiani L. The Monte Carlo method for the solution of charge transport in semiconductors with applications to covalent materials. Rev Mod Phys, 1983, 55(3): 645 doi: 10.1103/RevModPhys.55.645
[32]
Ahn W, Zhang H, Shen T et al. A predictive model for IC self-heating based on effective medium and image charge theories and its implications for interconnect and transistor reliability. IEEE Trans Electron Devices, 2017, 64(9): 3555 doi: 10.1109/TED.2017.2725742
[33]
Chang C W, Liu S E, Lin B L, et al. Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects. IEEE International Reliability Physics Symposium (IRPS), 2015: 2F.6.1
[34]
Wang N, Pi Y, Wang W, et al. Equivalent thermal conductivity model based full scale numerical simulation for thermal management in fan-out packages. IEEE Electronic Components and Technology Conference (ECTC), 2017: 2054
[35]
Pi Y, Wang W, Chen J, et al. Microfluidic cooling for distributed hot-spots. IEEE Electronic Components and Technology Conference (ECTC), 2016: 903
[36]
Jagannadham K. Thermal conductivity and interface thermal conductance in films of tungsten-tungsten silicide on Si. IEEE Trans Electron Devices, 2014, 61(6): 1950 doi: 10.1109/TED.2014.2318281
[37]
Takahashi T, Beppu N, Chen K, et al. Thermal-aware device design of nanoscale bulk/SOI FinFETs: Suppression of operation temperature and its variability. International Electron Devices Meeting (IEDM), 2011: 34.6.1
[38]
https://www.americanelements.com/hafnium-oxide-12055-23-1
[39]
Pop E, Sinha S, Goodson K E. Heat generation and transport in nanometer-scale transistors. Proc IEEE, 2006, 94(8): 1587 doi: 10.1109/JPROC.2006.879794
[40]
Pop E, Goodson K E. Thermal phenomena in nanoscale transistors. J Electron Pack, 2006, 128(2): 102 doi: 10.1115/1.2188950
[41]
Kolluri S, Endo K, Suzuki E, et al. Modeling and analysis of self-heating in FinFET devices for improved circuit and EOS/ESD performance. IEEE International Electron Devices Meeting, 2007: 177
[42]
Shrivastava M, Agrawal M, Mahajan S, et al. Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures. IEEE Trans Electron Devices, 2012, 59(5): 1353 doi: 10.1109/TED.2012.2188296
[43]
Filanovsky I M, Allam A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans Circuits Syst I, 2001, 48(7): 876 doi: 10.1109/81.933328
[44]
Wang R S, Liu H W, Huang R, et al. Experimental investigations on carrier transport in Si nanowire transistors: ballistic efficiency and apparent mobility. IEEE Trans Electron Devices, 2008, 55(11): 2960 doi: 10.1109/TED.2008.2005152
[45]
Lundstrom M, Ren Z. Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans Electron Devices, 2002, 49(1): 133 doi: 10.1109/16.974760
[46]
Prasad C, Jiang L, Singh D, et al. Self-heat reliability considerations on Intel’s 22 nm tri-gate technology. IEEE International Reliability Physics Symposium (IRPS), 2013: 5D.1.1
Fig. 1.  (Color online) The 14 nm-node Si bulk nFinFET structure used in this work.

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Fig. 2.  (Color online) Electro-thermal simulation framework used in this work.

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Fig. 3.  (Color online) (a) Intrinsic carrier density versus temperature. Data in Ref. [17] is shown for comparison. (b) Electro-phonon scattering rate versus kinetic energy at different temperatures. Data at TA = 300 K in Ref. [18] is shown for comparison.

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Fig. 4.  (Color online) Calibration of 14 nm-node Si nFinFET simulation results with DC experimental data.

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Fig. 5.  (Color online) The average electron energy distribution along the transport direction at Vgs = 0.7 V, Vds = 1 V and TA = 300 K. The thermal equilibrium carrier energy is 1.5 KBT (0.0389 eV).

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Fig. 6.  (Color online) (a) The input power Qinput and heat generation Qheat under different Vds and (b) the corresponding ratios of Qheat in Qinput at TA = 220, 300, 400 K and Vgs = 0.7 V.

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Fig. 7.  (Color online) (a) The input power Qinput and heat generation Qheat under different Vgs and (b) the corresponding ratios of Qheat in Qinput at TA = 220, 300, 400 K and Vds = 0.7 V.

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Fig. 8.  (Color online) (a) The average augments of lattice temperature and (b) the power densities along the transport direction comparing Vds = 0.7 V and Vds = 1 V at Vgs = 0.7 V, (c) the average augments of lattice temperature and (d) the power densities along the transport direction comparing Vgs = 0.7 V and Vgs = 1 V at Vds = 0.7 V. TA = 220, 300 and 400 K.

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Fig. 9.  (Color online) (a) Comparison of current densities considering SHE with those not considering SHE under different Vds and (b) the corresponding current degradation percentages caused by SHE at TA = 220, 300, 400 K and Vgs = 0.7 V.

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Fig. 11.  (Color online) (a) Comparison of ballistic factor Bsat considering SHE with that not considering SHE under different Vgs and (b) the corresponding degradation percentages of Bsat by SHE at TA = 220, 300, 400 K and Vds = 0.7 V.

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Fig. 10.  (Color online) (a) Comparison of current densities considering SHE with those not considering SHE under different Vgs and (b) the corresponding current degradation percentage by SHE at TA = 220, 300, 400 K and Vds = 0.7 V.

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Fig. 12.  (Color online) (a) Injection velocity υinj and (b) sheet density Qtop at the top of barrier ToB[45] under different Vgs with and without SHE at TA = 220, 300, 400 K and Vds = 0.7 V.

DownLoad: Full-Size Img PowerPoint
Fig. 13.  (Color online) The relationship of (a) T–TA and (b) thermal resistance Rth with Qinput at TA = 220, 300, 400 K when Vds = 0.7 V. Tpeak and Taverage respectively refer to the peak lattice temperature and the average lattice temperature.

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Fig. 14.  (Color online) The average augment of lattice temperature at the gate oxide region (Tgate–TA) with TA = 220, 300 and 400 K (a) under different Vgs at Vds = 0.7 V and (b) under different Vds at Vgs = 0.7 V. Tpeak–TA is plotted for comparison.

DownLoad: Full-Size Img PowerPoint

Table 1.   Structure parameters of the 14 nm-node nFinFET.

Strcuture
parameter 		Description Value
Hsd Raised S/D height 52 nm
Hstop Stop layer height 40 nm
Hsub Substrate layer height 4 μm
Hfin Fin height 42 nm
Lsd Raised S/D length 20 nm
Lext S/D length 10 nm
Lg Gate length 20 nm
Wpitch Fin pitch 42 nm
Wfin Fin width 8 nm
Nchannel Channel doping, p type 1 × 1015 cm−3
Nstop Stop layer doping, p type 2 × 1018 cm−3
Nsd Source/Drain doping, n type 1 × 1020 cm−3
Nsub Substrate doping, p type 1 × 1015 cm−3
EOT Equivalent oxide thickness 0.85 nm
Tox Gate oxide thickness 5.4 nm
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Table 2.   Optical phonon and inter-valley acoustic phonon in silicon.

η Phonon type DtK (1010 eV/m) $ \hbar \omega $ (meV) r
1 TA 0.47 12.1 g
2 LA 0.74 18.5 g
3 LO 10.23 62.0 g
4 TA 0.28 19.0 r
5 LA 1.86 47.4 r
6 TO 1.86 58.6 r
DownLoad: CSV

Table 3.   Thermal parameters used in this work.

Silicon thermal conductivity (anisotropic)
ky in Region (1–6) 15 Wm−1K−1
kx, kz in Region (1–6) 10 Wm−1K−1
Silicon thermal conductivity (isotropic)
k in Region (7) 148 Wm−1K−1
Oxide thermal conductivity (isotropic)
Trench oxide (SiO2) 1.4 Wm−1K−1
Gate oxide (HfO2) 1.1 Wm−1K−1
Contact thermal resistance
Gate 2.5 × 10−4 cm2K/W
Source/Drain/Substrate 0.5 × 10−4 cm2K/W
DownLoad: CSV
[1]
Pop E. Energy dissipation and transport in nanoscale devices. Nano Res, 2010, 3(3): 147 doi: 10.1007/s12274-010-1019-z
[2]
Semenov O, Vassighi A, Sachdev M. Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits. IEEE Trans Device Mater Rel, 2006, 6(1): 17 doi: 10.1109/TDMR.2006.870340
[3]
Shapiro A, Friedman E G. Power efficient level shifter for 16nm FinFET near threshold circuits. IEEE Trans VLSI Syst, 2016, 24(2): 774 doi: 10.1109/TVLSI.2015.2409051
[4]
Makovejev S, Planes N, Haond M, et al. Self-heating in 28 nm bulk and FDSOI. Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2015: 41
[5]
Bury E, Kaczer B, Linten D, et al. Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels. IEEE International Electron Devices Meeting (IEDM), 2016: 15.6.1
[6]
Bury E, Kaczer B, Mitard J, et al. Characterization of self-heating in high-mobility Ge FinFET pMOS devices. Symposium on VLSI Technology (VLSI Technology), 2015: T60
[7]
Wahab M A, Shin S H, Alam M A. 3D modeling of spatio-temporal heat-transport in III–V gate-all-around transistors allows accurate estimation and optimization of nanowire temperature. IEEE Trans Electron Devices, 2015, 62(11): 3595 doi: 10.1109/TED.2015.2478844
[8]
Liao M H, Hsieh C P, Lee C C. Systematic investigation of self-heating effect on CMOS logic transistors from 20 to 5 nm technology nodes by experimental thermoelectric measurements and finite element modeling. IEEE Trans Electron Devices, 2017, 64(2): 646 doi: 10.1109/TED.2016.2642404
[9]
Jin M, Liu C, Kim J, et al. Hot carrier reliability characterization in consideration of self-heating in FinFET technology. IEEE International Reliability Physics Symposium (IRPS), 2016: 2A-2-1
[10]
Jiang H, Shin S H, Liu X, et al. The impact of self-heating on HCI reliability in high-performance digital circuits. IEEE Device Lett, 2017, 38(4): 430 doi: 10.1109/LED.2017.2674658
[11]
Jiang H, Shen L, Shin S H, et al. Unified self-heating effect model for advanced digital and analog technology and thermal-aware lifetime prediction methodology. Symposium on VLSI Technology (VLSI Technology), 2017: T136
[12]
Si M W, Shin S H, Conrad N J, et al. Characterization and reliability of III–V gate-all-around MOSFETs. IEEE International Reliability Physics Symposium (IRPS), 2015: 4A.1.1
[13]
Jiang H, Liu X Y, Xu N, et al. Investigation of self-heating effect on hot carrier degradation in multiple-fin SOI FinFETs. IEEE Electron Device Lett, 2015, 36(12): 1258 doi: 10.1109/LED.2015.2487045
[14]
Vasileska D. Modeling self-heating in nanoscale devices. IEEE International Conference on Nanotechnology (IEEE-NANO), 2015: 200
[15]
Kamakura Y, Adisusilo I N, Kukita K, et al. Coupled Monte Carlo simulation of transient electron-phonon transport in small FETs. IEEE International Electron Devices Meeting (IEDM), 2014: 176
[16]
BSIM CMG, http://bsim.berkeley.edu/models/bsimcmg/, BSIM Group, 2015
[17]
Pierret R F. Semiconductor device fundamentals. Reading: Addison-Wesley, 1996
[18]
Fischetti M V, Laux S E. Monte Carlo analysis of electron transport in small semiconductor devices including band-structure and space-charge effects. Phys Rev B, 1988, 38(14): 9721 doi: 10.1103/PhysRevB.38.9721
[19]
Mohamed M, Aksamija Z, Vitale W, et al. A conjoined electron and thermal transport study of thermal degradation induced during normal operation of multigate transistors. IEEE Trans Electron Devices, 2014, 61(4): 976 doi: 10.1109/TED.2014.2306422
[20]
Gonzalez B, Palankovski V, Kosina H, et al. An analytical model for the electron energy relaxation time. International Association of Science and Technology for Development (IASTED), 1999: 367
[21]
Jeon J, Jhon H S, Kang M. Investigation of electrothermal behaviors of 5 nm Bulk FinFET. IEEE Trans Electron Devices, 2017, 64(12): 5284 doi: 10.1109/TED.2017.2766214
[22]
Wang L, Brown A R, Nedjalkov M, et al. Impact of self-heating on the statistical variability in bulk and SOI FinFETs. IEEE Trans Electron Devices, 2015, 62(7): 2106 doi: 10.1109/TED.2015.2436351
[23]
https://www.altera.com/products/common/temperature/ind-temp.html, 2017
[24]
Xie B Q, Bi J S, Li B, et al. The effect of cryogenic temperature characteristics on silicon-based devices and circuits. Microelectronics, 2015, 45(6): 789 (in Chinese)
[25]
Natarajan S, Agostinelli M, Akbar S, et al. A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size. IEEE International Electron Devices Meeting (IEDM), 2014: 71
[26]
ITRS. www.itrs2.net/itrs-reports.html, ITRS Reports, 2013
[27]
Wang J C, Du G, Wei K L, et al. Three-dimensional Monte Carlo simulation of bulk fin field effect transistor. Chin Phys B, 2012, 21(11): 117308 doi: 10.1088/1674-1056/21/11/117308
[28]
Wei K L, Egley J, Liu X Y, et al. Remote charge scattering: a full Coulomb interaction approach and its impact on silicon nMOS FinFETs with HfO2 gate dielectric. Sci China Inf Sci, 2014, 57(2): 022403
[29]
Du G, Liu X Y, Han R Q. Quantum Boltzmann equation solved by Monte Carlo method for nanoscale semiconductor devices. Chin Phys, 2006, 15(1): 177 doi: 10.1088/1009-1963/15/1/028
[30]
Du G, Liu X Y, Xia Z L, et al. Monte Carlo simulation of p- and n-channel GOI MOSFETs by solving the quantum Boltzmann equation. IEEE Trans Electron Devices, 2005, 52(10): 2258 doi: 10.1109/TED.2005.856806
[31]
Jacoboni C, Reggiani L. The Monte Carlo method for the solution of charge transport in semiconductors with applications to covalent materials. Rev Mod Phys, 1983, 55(3): 645 doi: 10.1103/RevModPhys.55.645
[32]
Ahn W, Zhang H, Shen T et al. A predictive model for IC self-heating based on effective medium and image charge theories and its implications for interconnect and transistor reliability. IEEE Trans Electron Devices, 2017, 64(9): 3555 doi: 10.1109/TED.2017.2725742
[33]
Chang C W, Liu S E, Lin B L, et al. Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects. IEEE International Reliability Physics Symposium (IRPS), 2015: 2F.6.1
[34]
Wang N, Pi Y, Wang W, et al. Equivalent thermal conductivity model based full scale numerical simulation for thermal management in fan-out packages. IEEE Electronic Components and Technology Conference (ECTC), 2017: 2054
[35]
Pi Y, Wang W, Chen J, et al. Microfluidic cooling for distributed hot-spots. IEEE Electronic Components and Technology Conference (ECTC), 2016: 903
[36]
Jagannadham K. Thermal conductivity and interface thermal conductance in films of tungsten-tungsten silicide on Si. IEEE Trans Electron Devices, 2014, 61(6): 1950 doi: 10.1109/TED.2014.2318281
[37]
Takahashi T, Beppu N, Chen K, et al. Thermal-aware device design of nanoscale bulk/SOI FinFETs: Suppression of operation temperature and its variability. International Electron Devices Meeting (IEDM), 2011: 34.6.1
[38]
https://www.americanelements.com/hafnium-oxide-12055-23-1
[39]
Pop E, Sinha S, Goodson K E. Heat generation and transport in nanometer-scale transistors. Proc IEEE, 2006, 94(8): 1587 doi: 10.1109/JPROC.2006.879794
[40]
Pop E, Goodson K E. Thermal phenomena in nanoscale transistors. J Electron Pack, 2006, 128(2): 102 doi: 10.1115/1.2188950
[41]
Kolluri S, Endo K, Suzuki E, et al. Modeling and analysis of self-heating in FinFET devices for improved circuit and EOS/ESD performance. IEEE International Electron Devices Meeting, 2007: 177
[42]
Shrivastava M, Agrawal M, Mahajan S, et al. Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures. IEEE Trans Electron Devices, 2012, 59(5): 1353 doi: 10.1109/TED.2012.2188296
[43]
Filanovsky I M, Allam A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans Circuits Syst I, 2001, 48(7): 876 doi: 10.1109/81.933328
[44]
Wang R S, Liu H W, Huang R, et al. Experimental investigations on carrier transport in Si nanowire transistors: ballistic efficiency and apparent mobility. IEEE Trans Electron Devices, 2008, 55(11): 2960 doi: 10.1109/TED.2008.2005152
[45]
Lundstrom M, Ren Z. Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans Electron Devices, 2002, 49(1): 133 doi: 10.1109/16.974760
[46]
Prasad C, Jiang L, Singh D, et al. Self-heat reliability considerations on Intel’s 22 nm tri-gate technology. IEEE International Reliability Physics Symposium (IRPS), 2013: 5D.1.1

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    Received: 22 January 2018 Revised: 13 February 2018 Online: Accepted Manuscript: 25 April 2018Uncorrected proof: 03 May 2018Published: 01 September 2018

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      Article Navigation >  Journal of Semiconductors  > 2018  >  39(9): 094011
      Longxiang Yin, Gang Du, Xiaoyan Liu. Impact of ambient temperature on the self-heating effects in FinFETs[J]. Journal of Semiconductors, 2018, 39(9): 094011. doi: 10.1088/1674-4926/39/9/094011 L X Yin, G Du, X Y Liu, Impact of ambient temperature on the self-heating effects in FinFETs[J]. J. Semicond., 2018, 39(9): 094011. doi: 10.1088/1674-4926/39/9/094011.Export: BibTex EndNote
      Citation:
      Longxiang Yin, Gang Du, Xiaoyan Liu. Impact of ambient temperature on the self-heating effects in FinFETs[J]. Journal of Semiconductors, 2018, 39(9): 094011. doi: 10.1088/1674-4926/39/9/094011

      L X Yin, G Du, X Y Liu, Impact of ambient temperature on the self-heating effects in FinFETs[J]. J. Semicond., 2018, 39(9): 094011. doi: 10.1088/1674-4926/39/9/094011.
      Export: BibTex EndNote
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      Impact of ambient temperature on the self-heating effects in FinFETs

      doi: 10.1088/1674-4926/39/9/094011

      • Institute of Microelectronics, Peking University, Beijing 100871, China

      Funds:

      Project supported by the National Key Technology Research and Development Program of China (No. 2016YFA0202101), the National Natural Science Foundation of China (Nos. 61421005, 61604005), and the National High-Tech R&D Program (863 Program) (No. 2015AA016501). The simulation was carried out at National Supercomputer Center in Tianjin, with TianHe-1(A).

      More Information
      • Corresponding author: Email: xyliu@ime.pku.edu.cn
      • Received Date: 2018-01-22
      • Revised Date: 2018-02-13
      • Published Date: 2018-09-01

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