J. Semicond. > Volume 37 > Issue 5 > Article Number: 055008

Negative voltage bandgap reference with multilevel curvature compensation technique

Xi Liu 1, , , Qian Liu 1, 2, , Xiaoshi Jin 1, , Yongrui Zhao 2, 3, and Jong-Ho Lee 4,

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Abstract: A novel high-order curvature compensation negative voltage bandgap reference (NBGR) based on a novel multilevel compensation technique is introduced. Employing an exponential curvature compensation (ECC) term with many high order terms in itself, in a lower temperature range (TR) and a multilevel curvature compensation (MLCC) term in a higher TR, a flattened and better effect of curvature compensation over the TR of 165 ℃ (-40 to 125 ℃ ) is realised. The MLCC circuit adds two convex curves by using two sub-threshold operated NMOS. The proposed NBGR implemented in the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm BCD technology demonstrates an accurate voltage of -1.183 V with a temperature coefficient (TC) as low as 2.45 ppm/℃ over the TR of 165 ℃ at a -5.0 V power supply; the line regulation is 3 mV/V from a -5 to -2 V supply voltage. The active area of the presented NBGR is 370 × 180 μm2.

Key words: negative voltage bandgap referenceECCmultilevel curvature-compensationTCline regulation

Abstract: A novel high-order curvature compensation negative voltage bandgap reference (NBGR) based on a novel multilevel compensation technique is introduced. Employing an exponential curvature compensation (ECC) term with many high order terms in itself, in a lower temperature range (TR) and a multilevel curvature compensation (MLCC) term in a higher TR, a flattened and better effect of curvature compensation over the TR of 165 ℃ (-40 to 125 ℃ ) is realised. The MLCC circuit adds two convex curves by using two sub-threshold operated NMOS. The proposed NBGR implemented in the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm BCD technology demonstrates an accurate voltage of -1.183 V with a temperature coefficient (TC) as low as 2.45 ppm/℃ over the TR of 165 ℃ at a -5.0 V power supply; the line regulation is 3 mV/V from a -5 to -2 V supply voltage. The active area of the presented NBGR is 370 × 180 μm2.

Key words: negative voltage bandgap referenceECCmultilevel curvature-compensationTCline regulation



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[1]

Su Kai, Gong Min, Qin Huaibin. A multiple transistor combination low-voltage curvature-corrected bandgap reference[J]. Journal of Semiconductors, 2013, 34: 065010.

[2]

Liao Jun, Zhao Yiqiang, Geng Junfeng. A sub-1 V high-precision CMOS bandgap voltage reference[J]. Journal of Semiconductors, 2012, 33: 025014.

[3]

Zhou Z, Shi Y, Huang Z. A 1.6 V 25 μA 5 ppm/℃ curvature compensated bandgap reference[J]. IEEE Trans Circuits Syst, 2012, 59: 677.

[4]

Ma B, Yu F Q. A novel 1.2 V 4.5 ppm/℃ curvature compensated CMOS bandgap reference[J]. IEEE Trans Circuits Syst, 2014, 61: 1026.

[5]

Li J H, Zhang X, Yu M. A 1.2 V piecewise curvature-corrected bandgap reference in 0.5 μm CMOS Process[J]. IEEE Trans Very Large Scale Integr Syst, 2011, 19: 111.

[6]

Zhang Zhu, Sun Y, Huang Z. 1 ppm/℃ bandgap with multipoint curvature-compensation technique for HVIC[J]. Electron Lett, 2014, 50: 1908.

[7]

Lee I, Kim G, Kim W. Exponential curvature compensated BiCMOS bandgap references[J]. IEEE J Solid-State Circuits, 1994, 29: 1396.

[8]

Zhu Zhengyong. Semiconductor Integrated Circuits. 2nd edition[J]. Beijing: Tsinghua University Press, 2009.

[9]

Sze S M. Ng K K. Physics of semiconductor devices. 3rd edition[J]. Hoboken, New Jersey, USA: John Wiley & Sons, Inc, 2007.

[10]

Yannis T. Operation and modelling of the MOS transistor. 2nd ed. Boston[J]. USA: McGraw Hill, 1999.

[11]

Razavi B. Design of analog CMOS integrated circuits[J]. McGraw Hill, 2002.

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X Liu, Q Liu, X S Jin, Y R Zhao,J H Lee. Negative voltage bandgap reference with multilevel curvature compensation technique[J]. J. Semicond., 2016, 37(5): 055008. doi: 10.1088/1674-4926/37/5/055008.

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Manuscript received: 09 September 2015 Manuscript revised: Online: Published: 01 May 2016

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