J. Semicond. > Volume 37 > Issue 5 > Article Number: 054003

Performance analysis of charge plasma based dual electrode tunnel FET

Sunny Anand , S. Intekhab Amin and R. K. Sarin

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Abstract: This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (ION ~ 0.56 mA/μm), ION/IOFF ratio ~ 9.12 × 1013 and an average subthreshold swing (AV-SS ~ 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.

Key words: band to band tunneling (BTBT)charge plasmadoping-less tunnel field effect transistor (DLTFET)average subthreshold swingdrain induced barrier lowering (DIBL)

Abstract: This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (ION ~ 0.56 mA/μm), ION/IOFF ratio ~ 9.12 × 1013 and an average subthreshold swing (AV-SS ~ 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.

Key words: band to band tunneling (BTBT)charge plasmadoping-less tunnel field effect transistor (DLTFET)average subthreshold swingdrain induced barrier lowering (DIBL)



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Yan R H, Abbas O, Lee K F. Scaling the Si MOSFET: from bulk to SOI to bulk[J]. IEEE Trans Electron Devices, 1992, 39(7): 1704.

[2]

Young K K. Short-channel effect in fully-depleted SOI MOS- ewpage FETs[J]. IEEE Trans Electron Devices, 1989, 36(2): 399.

[3]

Colinge J P, Lee C W, Afzalian A. Nanowire transistors without junctions[J]. Nature Nanotechnol, 2010, 5(3): 225.

[4]

Lu L, Mohata D, Datta S. Scaling length theory of double-gate interband tunnel field-effect transistors[J]. IEEE Trans Electron Devices, 2012, 59(4): 902.

[5]

Bal P, Akram M W, Mondal P. Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)[J]. J Comput Electron, 2013, 12: 782.

[6]

Boucart K, Ionescu A M. Double gate tunnel FET high-k gate dielectric[J]. IEEE Trans Electron Devices, 2007, 54(7): 1725.

[7]

Verhulst A S, Vandenberghe W G, Maex K. Complementary silicon-based hetero-structure tunnel-FETs with high tunnel rates[J]. IEEE Electron Device Lett, 2008, 29(12): 1398.

[8]

Patel N, Ramesha A, Mahapatra S. Drive current boosting of n-type tunnel FET with strained SiGe layer at source[J]. Microelectron J, 2008, 39(12): 1671.

[9]

Lee M L, Eugene A F, Mayank T B. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors[J]. J Appl Phys, 2005, 97: 011101.

[10]

Damrongplasit N, Shin C, Kim S H. Study of random dopant fluctuation effects in germanium-source tunnel FETs[J]. IEEE Trans Electron Devices, 2011, 58(10): 3541.

[11]

Leung G, Chui O C. Stochastic variability in silicon double gate lateral tunnel field-effect transistors[J]. IEEE Trans Electron Devices, 2013, 60(1): 84.

[12]

Kumar M J, Janardhanan S. Doping-less tunnel field effect transistor: design and investigation[J]. IEEE Trans Electron Devices, 2013, 60(10): 3285.

[13]

Hueting R J E, Rajasekharan B, Salm C. The charge plasma p-n diode[J]. IEEE Electron Device Lett, 2008, 29(12): 1367.

[14]

Sahu C, Singh J. Charge-plasma based process variation immune junctionless transistor[J]. IEEE Trans Electron Device Lett, 2014, 35(3): 411.

[15]

Kumar M J, Nadda K. Bipolar charge-plasma transistor: a novel three terminal device[J]. IEEE Trans Electron Devices, 2012, 59(4): 962.

[16]

Rajasekharan B, Hueting R J E, Salm C. Fabrication and characterization of the charge-plasma diode[J]. IEEE Electron Device Lett, 2010, 31(6): 528.

[17]

ATLAS . Device Simulation Software[J]. Silvaco Int., Santa Clara, CA, USA, 2012.

[18]

Omura Y, Horiguchi S, Tabe M. Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs[J]. IEEE Trans Electron Devices, 1993, 14(12): 569.

[19]

Saurabh S, Kumar M J. Novel attributes of a dual material gate nanoscale tunnel field-effect transistor[J]. IEEE Trans Electron Devices, 2011, 58(2): 404.

[20]

Lide D R. CRC handbook on chemistry and physics[J]. 89th ed. Taylor & Francis, London, 2008: 12.

[21]

Cui N, Liang R, Xu J. Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation[J]. Appl Phys Lett, 2011, 98(14): 142105.

[22]

Knoch J, Appenzeller J. A novel concept for field-effect transistors-the tunneling carbon nanotube FET[J]. IEEE 63rd Device Research Conference (DRC) Digest, 2005, 1: 153.

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S Anand, S. I. Amin, R. K. Sarin. Performance analysis of charge plasma based dual electrode tunnel FET[J]. J. Semicond., 2016, 37(5): 054003. doi: 10.1088/1674-4926/37/5/054003.

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Manuscript received: 12 August 2015 Manuscript revised: Online: Published: 01 May 2016

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