ARTICLES
Chao Fan, Yahua Ran and Liqun Ye
Corresponding author: Chao Fan, fanchao41@126.com
Abstract: A proposed inductive-phase-compensation ultra wideband CMOS digital T-type attenuator design based on an analysis of minimising phase errors is presented in this letter. In a standard CMOS technology, the proposed attenuator is analytically demonstrated to have low phase errors due to the inductive-phase-compensation network. A design equation is inferred and a wide-band 4dB attenuation bit digital attenuator with low phase errors is designed as a test vehicle for the proposed approach.
Key words: ultra-wideband, digital T-type attenuator, low phase error, inductive-phase-compensation, CMOS
| [1] |
Sadhu B, Tousi Y, Hallin J, et al. A 28-GHz 32-element TRX phased-array IC with concurrent dual-polarized operation and orthogonal phase and gain control for 5G communications. IEEE J Solid State Circuits, 2017, 52, 3373 doi: 10.1109/JSSC.2017.2766211
|
| [2] |
Min B W, Rebeiz G M. A 10–50-GHz CMOS distributed step attenuator with low loss and low phase imbalance. IEEE J Solid State Circuits, 2007, 42, 2547 doi: 10.1109/JSSC.2007.907205
|
| [3] |
Ku B H, Hong S. 6-bit CMOS digital attenuators with low phase variations for X-band phased-array systems. IEEE Trans Microw Theory Tech, 2010, 58, 1651 doi: 10.1109/TMTT.2010.2049691
|
| [4] |
Zhang L, Zhao C X, Zhang X N, et al. A CMOS K-band 6-bit attenuator with low phase imbalance for phased array applications. IEEE Access, 2017, 5, 19657 doi: 10.1109/ACCESS.2017.2750203
|
| [5] |
Ciccognani W, Giannini F, Limiti E, et al. Compensating for parasitic phase shift in microwave digitally controlled attenuators. Electron Lett, 2008, 44, 743 doi: 10.1049/el:20080987
|
| [6] |
Sun P P. Analysis of phase variation of CMOS digital. Electron Lett, 2014, 50, 1912 doi: 10.1049/el.2014.2640
|
| [7] |
Gu P, Zhao D X, You X H. A DC-50 GHz CMOS switched-type attenuator with capacitive compensation technique. IEEE Trans Circuits Syst I, 2020, 67, 3389 doi: 10.1109/TCSI.2020.2999094
|
| [8] |
Zhao C X, Zeng X, Zhang L, et al. A 37–40-GHz low-phase-imbalance CMOS attenuator with tail-capacitor compensation technique. IEEE Trans Circuits Syst I, 2020, 67, 3400 doi: 10.1109/TCSI.2020.2990705
|
| [9] |
Yang C C, Yan N, Li T, et al. Design of a wideband CMOS digital step attenuator with high accuracy and low phase error. 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology, 2020, 1 doi: 10.1109/ICSICT49897.2020.9278175
|
| [10] |
Koh K J, Rebeiz G M. 0.13-μm CMOS phase shifters for X-, Ku-, and K-band phased arrays. IEEE J Solid State Circuits, 2007, 42, 2535 doi: 10.1109/JSSC.2007.907225
|
Table 1. Comparison of attenuation 4 dB bit attenuators.
| Parameter | Ref. [3] | Ref. [4] | Ref. [5] | Typical | This paper |
| Tech. | 0.18 μm CMOS | 0.18 μm CMOS | 0.18 μm p-HEMT | 0.13 μm CMOS | 0.13 μm CMOS |
| BW (GHz) | 8–12 | 19–21 | 8.5–11.5 | 5–25 | 5–25 |
| IL (dB) | 8.7 | 8 | 0.8 | 2 | 2.3 |
| Phase diff. (°) | 3.5 | 3.8 | 2 | 6 | 1 |
| Return loss (dB) | 10 | 12 | 20 | 10 | 10 |
| Area (μm2) | 1250 × 400 | 1300 × 340 | — | 180 × 60 | 180 × 60 |
| Corr. structure | Ind. corr. (170 pH) | Cap. orr. | Cap. corr. | No | Ind. corr. (20 pH) |
DownLoad: CSV
| [1] |
Sadhu B, Tousi Y, Hallin J, et al. A 28-GHz 32-element TRX phased-array IC with concurrent dual-polarized operation and orthogonal phase and gain control for 5G communications. IEEE J Solid State Circuits, 2017, 52, 3373 doi: 10.1109/JSSC.2017.2766211
|
| [2] |
Min B W, Rebeiz G M. A 10–50-GHz CMOS distributed step attenuator with low loss and low phase imbalance. IEEE J Solid State Circuits, 2007, 42, 2547 doi: 10.1109/JSSC.2007.907205
|
| [3] |
Ku B H, Hong S. 6-bit CMOS digital attenuators with low phase variations for X-band phased-array systems. IEEE Trans Microw Theory Tech, 2010, 58, 1651 doi: 10.1109/TMTT.2010.2049691
|
| [4] |
Zhang L, Zhao C X, Zhang X N, et al. A CMOS K-band 6-bit attenuator with low phase imbalance for phased array applications. IEEE Access, 2017, 5, 19657 doi: 10.1109/ACCESS.2017.2750203
|
| [5] |
Ciccognani W, Giannini F, Limiti E, et al. Compensating for parasitic phase shift in microwave digitally controlled attenuators. Electron Lett, 2008, 44, 743 doi: 10.1049/el:20080987
|
| [6] |
Sun P P. Analysis of phase variation of CMOS digital. Electron Lett, 2014, 50, 1912 doi: 10.1049/el.2014.2640
|
| [7] |
Gu P, Zhao D X, You X H. A DC-50 GHz CMOS switched-type attenuator with capacitive compensation technique. IEEE Trans Circuits Syst I, 2020, 67, 3389 doi: 10.1109/TCSI.2020.2999094
|
| [8] |
Zhao C X, Zeng X, Zhang L, et al. A 37–40-GHz low-phase-imbalance CMOS attenuator with tail-capacitor compensation technique. IEEE Trans Circuits Syst I, 2020, 67, 3400 doi: 10.1109/TCSI.2020.2990705
|
| [9] |
Yang C C, Yan N, Li T, et al. Design of a wideband CMOS digital step attenuator with high accuracy and low phase error. 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology, 2020, 1 doi: 10.1109/ICSICT49897.2020.9278175
|
| [10] |
Koh K J, Rebeiz G M. 0.13-μm CMOS phase shifters for X-, Ku-, and K-band phased arrays. IEEE J Solid State Circuits, 2007, 42, 2535 doi: 10.1109/JSSC.2007.907225
|
Article views: 1103 Times PDF downloads: 62 Times Cited by: 0 Times
Received: 19 August 2021 Revised: 11 December 2021 Online: Accepted Manuscript: 15 January 2022Uncorrected proof: 24 January 2022Published: 10 March 2022
| Citation: |
Chao Fan, Yahua Ran, Liqun Ye. Ultra wideband CMOS digital T-type attenuator with low phase errors[J]. Journal of Semiconductors, 2022, 43(3): 032401. doi: 10.1088/1674-4926/43/3/032401
C Fan, Y H Ran, L Q Ye, Ultra wideband CMOS digital T-type attenuator with low phase errors[J]. J. Semicond., 2022, 43(3): 032401. doi: 10.1088/1674-4926/43/3/032401.
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|
| [1] |
Sadhu B, Tousi Y, Hallin J, et al. A 28-GHz 32-element TRX phased-array IC with concurrent dual-polarized operation and orthogonal phase and gain control for 5G communications. IEEE J Solid State Circuits, 2017, 52, 3373 doi: 10.1109/JSSC.2017.2766211
|
| [2] |
Min B W, Rebeiz G M. A 10–50-GHz CMOS distributed step attenuator with low loss and low phase imbalance. IEEE J Solid State Circuits, 2007, 42, 2547 doi: 10.1109/JSSC.2007.907205
|
| [3] |
Ku B H, Hong S. 6-bit CMOS digital attenuators with low phase variations for X-band phased-array systems. IEEE Trans Microw Theory Tech, 2010, 58, 1651 doi: 10.1109/TMTT.2010.2049691
|
| [4] |
Zhang L, Zhao C X, Zhang X N, et al. A CMOS K-band 6-bit attenuator with low phase imbalance for phased array applications. IEEE Access, 2017, 5, 19657 doi: 10.1109/ACCESS.2017.2750203
|
| [5] |
Ciccognani W, Giannini F, Limiti E, et al. Compensating for parasitic phase shift in microwave digitally controlled attenuators. Electron Lett, 2008, 44, 743 doi: 10.1049/el:20080987
|
| [6] |
Sun P P. Analysis of phase variation of CMOS digital. Electron Lett, 2014, 50, 1912 doi: 10.1049/el.2014.2640
|
| [7] |
Gu P, Zhao D X, You X H. A DC-50 GHz CMOS switched-type attenuator with capacitive compensation technique. IEEE Trans Circuits Syst I, 2020, 67, 3389 doi: 10.1109/TCSI.2020.2999094
|
| [8] |
Zhao C X, Zeng X, Zhang L, et al. A 37–40-GHz low-phase-imbalance CMOS attenuator with tail-capacitor compensation technique. IEEE Trans Circuits Syst I, 2020, 67, 3400 doi: 10.1109/TCSI.2020.2990705
|
| [9] |
Yang C C, Yan N, Li T, et al. Design of a wideband CMOS digital step attenuator with high accuracy and low phase error. 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology, 2020, 1 doi: 10.1109/ICSICT49897.2020.9278175
|
| [10] |
Koh K J, Rebeiz G M. 0.13-μm CMOS phase shifters for X-, Ku-, and K-band phased arrays. IEEE J Solid State Circuits, 2007, 42, 2535 doi: 10.1109/JSSC.2007.907225
|
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