Fig. 1.
Band diagram for MOS structure with positive gate bias, indicating main processes for radiation-induced charge generation.
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Yanfei Li, Shaoli Zhu, Jianwei Wu, Genshen Hong, Zheng Xu. Research for radiation-hardened high-voltage SOI LDMOS[J]. Journal of Semiconductors, 2019, 40(5): 052401. doi: 10.1088/1674-4926/40/5/052401
Y F Li, S L Zhu, J W Wu, G S Hong, Z Xu, Research for radiation-hardened high-voltage SOI LDMOS[J]. J. Semicond., 2019, 40(5): 052401. doi: 10.1088/1674-4926/40/5/052401.
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Research for radiation-hardened high-voltage SOI LDMOS
doi: 10.1088/1674-4926/40/5/052401
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Abstract
Based on the silicon-on-insulator (SOI) technology and radiation-hardened silicon gate (RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET (LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose (TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner, and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad (Si).-
Keywords:
- radiation-hardened,
- RGS,
- total ion dose,
- threshold voltage shift
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References
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