J. Semicond. > Volume 37 > Issue 5 > Article Number: 055004

A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

Bo Zhong , and Zhangming Zhu

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Abstract: A 0.1-1.5 GHz, 3.07 pS root mean squares (RMS) jitter, area efficient phase locked loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter (LPF) is significantly decreased by implementing a dual path charge pump (CP) technique in this PLL. Subject to specified power consumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator (VCO), CP and phase/frequency detector (PFD) in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal (MOM) capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.

Key words: phase lock loopfreqency synthesizerdual path charge pumpCMOS

Abstract: A 0.1-1.5 GHz, 3.07 pS root mean squares (RMS) jitter, area efficient phase locked loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter (LPF) is significantly decreased by implementing a dual path charge pump (CP) technique in this PLL. Subject to specified power consumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator (VCO), CP and phase/frequency detector (PFD) in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal (MOM) capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.

Key words: phase lock loopfreqency synthesizerdual path charge pumpCMOS



References:

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[1]

Navid R, Chen E H, Hossain M. A 40 Gb/s serial link transceiver in 28 nm CMOS technology[J]. IEEE J Solid-State Circuits, 2015, 50(4): 1.

[2]

Fujimori I. Evolution of multi-gigabit wireline transceivers in CMOS[J]. Compd Semicond Integr Circuit Symp, 2014: 9.

[3]

Gb A, Using S, Loop P. A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop[J]. Cust Integr Circuits Conf, 2014: 8.

[4]

Cheng K H, Hung C L, Gong C S A. A 0.9- to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes[J]. IEEE Trans Circuits Syst II, 2014, 61(8): 559.

[5]

Qin Peng, Li Jinbo, Kang Jian. Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm[J]. Journal of Semiconductors, 2014, 35(9): 095007.

[6]

Tang Lu, Wang Zhigong, Xue Hong. A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits[J]. Journal of Semiconductors, 2010, 31(5): 055008.

[7]

Zhang Hui, Yang Haigang, Wang Yu. A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA[J]. Journal of Semiconductors, 2011, 32(4): 045010.

[8]

Meng X, Huang L, Chen L. Area efficiency PLL design using capacitance multiplication based on self-biased architecture[J]. IEEE Int Symp Radio-Frequency Integr Technol, 2011: 193.

[9]

Lim P J. An area-efficient PLL architecture in 90-nm CMOS[J]. IEEE Symposium on VLSI Circuits, 2005: 48.

[10]

Park J, Liu J F, Carley L R. A 1-V, 1.4-2.5 GHz charge-pump-less PLL for a phase interpolator based CDR[J]. Cust Integr Circuits Conf, 2007: 281.

[11]

Kumar A, Nagaraj K. Area-efficient low-noise low-spur architecture for an analog PLL working from a low frequency reference[J]. IEEE Trans Circuits Syst II, 2012, 59(6): 331.

[12]

Maxim A, Scott B, Member A. A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter[J]. IEEE J Solid-State Circuits, 2001, 36(11): 1673.

[13]

Loke A L S, Member S, Barnes R K. A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking[J]. IEEE J Solid-State Circuits, 2006, 41(8): 1894.

[14]

Shinagawa M, Akazawa Y, Wakimoto T. Jitter analysis of high-speed sampling systems[J]. IEEE J Solid-State Circuits, 1990, 25(1): 220.

[15]

Hong D, Ong C, Cheng K T. BER estimation for serial links based on jitter spectrum and clock recovery characteristics[J]. IEEE Int Test Conference, 2004: 1138.

[16]

Pellerano S, Levantino S, Samori C. A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider[J]. IEEE J Solid-State Circuits, 2004, 39(2): 378.

[17]

Lin T H, Ti C L, Liu Y H. Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs[J]. IEEE Trans Circuits Syst I, 2009, 56(5): 877.

[18]

Homayoun A, Razavi B. Analysis of phase noise in phase/frequency detectors[J]. IEEE Trans Circuits Systems I, 2013, 60(3): 529.

[19]

Jitter L, Synthesizer L F, Keady A. 12 MHz to 5800 MHz fully integrated, dual path tuned, low jitter, LC-PLL frequency synthesizer[J]. IET Irish Signals Syst Conf (ISSC), 2012: 1.

[20]

Abidi A A. Phase noise and jitter in CMOS ring oscillators[J]. IEEE J Solid-State Circuits, 2006, 41(8): 1803.

[21]

Razavi B. A study of phase noise in CMOS oscillators[J]. IEEE J Solid-State Circuits, 1996, 31(3): 331.

[22]

Hajimiri A, Limotyrakis S, Lee T H. Jitter and phase noise in ring oscillators[J]. IEEE J Solid-State Circuits, 1999, 34(6): 790.

[23]

Min S, Copani T, Kiaei S. A 90-nm CMOS 5-GHz ring-oscillator PLL with delay-discriminator-based active phase-noise cancellation[J]. IEEE J Solid-State Circuits, 2013, 48(5): 1151.

[24]

Yuan H, Guo Y, Ma Z. A 40 nm/65 nm process adaptive low jitter phase-locked loop[J]. 14th Int Symp Integr Circuits (ISIC), 2014: 500.

[25]

Vamvakos S D, Gauthier C R, Rao C. A 2.488-11.2 Gb/s multi-protocol SerDes in 40 nm low-leakage CMOS for FPGA applications[J]. Midwest Symposium on Circuits and Systems (MWSCAS), 2012: 5.

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B Zhong, Z M Zhu. A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process[J]. J. Semicond., 2016, 37(5): 055004. doi: 10.1088/1674-4926/37/5/055004.

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Manuscript received: 26 August 2015 Manuscript revised: Online: Published: 01 May 2016

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