J. Semicond. > Volume 37 > Issue 5 > Article Number: 055001

DOIND: a technique for leakage reduction in nanoscale domino logic circuits

Ambika Prasad Shah 1, , Vaibhav Neema 1, and Shreeniwas Daulatabad 2,

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Abstract: A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.

Key words: deep submicronDOIND logicdomino logicevaluationprechargesubthreshold leakage

Abstract: A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.

Key words: deep submicronDOIND logicdomino logicevaluationprechargesubthreshold leakage



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Al-Hertani H, Al-Khalili D, Rozon C. UDSM subthreshold leakage model for NMOS transistor stacks[J]. Microelectron J, 2008, 39(12): 1809.

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Deepaksubramanyam B S, Nunez A. Analysis of subthreshold leakage reduction in CMOS digital circuits[J]. Proceeding of 50th Midwest Symposium on Circuits and Systems (MWSCAS), 2004: 1400.

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Piguet C. Low power electronics design[J]. CRC Press, 2005.

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Shah A P, Neema V, Daulatabad S. A novel leakage reduction DOIND approach for nanoscale domino logic circuits[J]. Proceedings of IEEE International Conference on Contemporary Computing (IC3), 2015: 434.

[1]

Sharma V K, Pattanaik M, Raj B. INDEP approach for leakage reduction in nanoscale CMOS circuits[J]. International Journal of Electronics, 2015, 102(2): 200.

[2]

Kim S H, Mooney V J. Sleepy keeper: a new approach to low leakage power VLSI design[J]. IFIP International Conference on very Large Scale Integration, 2006: 367.

[3]

Kao J. Dual threshold voltage domino logic[J]. Proceedings of 25th European Conference on Solid State Circuits, 1999: 118.

[4]

Kursun V, Friedman E G. Sleep switch dual threshold voltage domino logic with reduced standby leakage current[J]. IEEE Trans VLSI Syst, 2004, 12(5): 485.

[5]

Kursun V, Friedman E G. Domino logic with variable threshold voltage keeper[J]. IEEE Trans VLSI Syst, 2003, 11(6): 1080.

[6]

Heo S, Asanovic K. Leakage biased domino circuits for dynamic fine-grain leakage reduction[J]. Symposium on VLSI Circuits, Honolulu, 2002: 316.

[7]

Pandey A K, Mishra R A, Nagaria R K. Leakage power analysis of domino XOR gate[J]. ISRN Electron, 2013, 2013(7): 1.

[8]

Chen Z, Johnson M, Wei L. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks[J]. International Symposium on Low Power Electronics and Design, 1998: 239.

[9]

Wong J, Gong N, Hou L. Low power and high performance CMOS XOR/XNOR gate design[J]. Microelectron Eng, 2011, 88(8): 2781.

[10]

Mutoh S, Douseki T, Matsuya Y. 1-V power supply high speed digital circuit technology with multithreshold voltage CMOS[J]. IEEE J Solid-State Circuits, 2011, 30(8): 847.

[11]

Powell M, Yang S H, Falsafi B. Gated-Vdd: a circuit technique to reduce leakage in deep submicron cache memories[J]. International Symposium on Low Power Electronics and Design, 2000: 90.

[12]

Moradi F, Peiravi A, Mahmoodi H. A New leakage tolerant design for high fan-in domino circuits[J]. Proceedings of The 16th International Conference on Microelectronics (ICM 2004), 2004: 493.

[13]

Anis M H, Allam M W, Elmasry M I. Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies[J]. IEEE Trans VLSI Syst, 2002, 10(2): 71.

[14]

Ding L, Mazumder P. On Circuit technique to improve noise immunity of CMOS dynamic logic[J]. IEEE Trans VLSI Syst, 2004, 12(9): 910.

[15]

Al-Hertani H, Al-Khalili D, Rozon C. UDSM subthreshold leakage model for NMOS transistor stacks[J]. Microelectron J, 2008, 39(12): 1809.

[16]

Deepaksubramanyam B S, Nunez A. Analysis of subthreshold leakage reduction in CMOS digital circuits[J]. Proceeding of 50th Midwest Symposium on Circuits and Systems (MWSCAS), 2004: 1400.

[17]

Piguet C. Low power electronics design[J]. CRC Press, 2005.

[18]

Shah A P, Neema V, Daulatabad S. A novel leakage reduction DOIND approach for nanoscale domino logic circuits[J]. Proceedings of IEEE International Conference on Contemporary Computing (IC3), 2015: 434.

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A P Shah, V Neema, S Daulatabad. DOIND: a technique for leakage reduction in nanoscale domino logic circuits[J]. J. Semicond., 2016, 37(5): 055001. doi: 10.1088/1674-4926/37/5/055001.

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Manuscript received: 19 August 2015 Manuscript revised: Online: Published: 01 May 2016

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