INVITED REVIEW PAPERS

Concept and design of super junction devices

Bo Zhang, Wentong Zhang, Ming Qiao, Zhenya Zhan and Zhaoji Li

+ Author Affiliations

 Corresponding author: Bo Zhang, Email: zhangbo@uestc.edu.cn

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Abstract: The super junction (SJ) has been recognized as the " milestone” of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer (VSL). The basic structure of the SJ is a typical junction-type VSL (J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL (R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the J-VSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional " silicon limit” relationship of RonVB2.5, showing a quasi-linear relationship of RonVB1.03.

Key words: super junctionsilicon limitpower semiconductor devicedesign theory



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Fig. 1.  Structure of the SJ MOSFET.

Fig. 2.  Concepts of the charge electric field Eq(x, y) and the potential electric field Ep.

Fig. 3.  (Color online) The equal-potential relationship of the SJ.

Fig. 4.  (Color online) Comparisons between the experiments of the SJ MOSFETs.

Fig. 5.  The critical process steps of the SJ. (a) The multi-epitaxy process with the P-type doping. (b) The multi-epitaxy process with both the P- and N-type dopings. (c) The multi-implant process with different energies. (d) The deep trench etch process with the doping methods of. (e) The epitaxy process. (f) The angled implant process. (g) The trench-wall gas phase doping process.

Fig. 6.  New structures based on the SJ concept. (a) The partial SJ MOSFET. (b) the SJ IGBT; (c) the SJ MOSFET with the integrated Schottky contact. (d) The SJ Schottky barrier diode (SBD). (e) The SJ junction barrier Schottky rectifier (JBS). (f) OB (oxide-bypassed) MOSFET. (g) The high-k diode; (h) the SJ high-k device.

Fig. 7.  New structures of the lateral SJ devices. (a) The CBSLOP LDMOS. (b) The SJ LDMOS on the sapphire substrate. (c) The unbalanced SJ device. (d) The partial SJ LDMOS; the SJ LDMOS with (e) the N-buffer layer. (f) The non-uniform N-buried layer. (g) The step doping buried layer. (h) The surface step doped N layer, (i) the non-full depleted charge compensation layer.

Fig. 8.  (Color online) The equal potential lines of the SJ MOSFET with Ld = 52 μm, W = 2 μm and N = 1.53 × 1016 cm−3 in (a) the turn on process (Vd = 45 V) and (b) turn-off process (Vd = 15 V).

Fig. 9.  (Color online) (a) Normalized factor η for the SJ structure with different aspect ratios Ld/W. γ > 1 represents the SJ structure in the NFD mode and γ ≤ 1 corresponds to the SJ structure in the FD mode. (b) The NFD and FD concepts of the SJ structure. δ is the length of the neutral region in each pillar of the SJ structure at breakdown. For the NFD mode, δ > 0 and for the FD mode, δ = 0.

Fig. 10.  (Color online) The breakdown path of SJ device and the electric field along the path.

Fig. 11.  (Color online) Different optimization methods along R-well.

Fig. 12.  (Color online) Comparison of RonVB relationships between the Ron, min optimization and other optimizations.

Fig. 13.  (Color online) Concept of the equivalent substrate (ES). (a) The lateral SJ device. (b) The concept of the ES. (c) The optimized lateral SJ.

Fig. 14.  (Color online) Comparison of Ron for different SJ-LDMOS devices. The experimental results have been marked with stars. The devices connected with the dashed line have the same W, H, and VB.

[1]
Zhang B, Zhang W T, Qiao M, et al. Theory and optimization of the power super junction device. Sci Sin-Phys Mech Astron, 2016, 46: 107302 (in Chinese)
[2]
Zhang B, Luo X R, Li Z J. Electric field optimization technology for power semiconductor devices. Chengdu: UESTC Press, 2016 (in Chinese)
[3]
Chen X B. Superjunction device. Power Electron, 2008, 42(12): 2 (in Chinese)
[4]
Chen X B. Semiconductor power devices with alternating conductivity type high-voltage breakdown region. US Patient, US5216275, 1993
[5]
Chen X B, Mawby P A, Board K, et al. Theory of a novel voltage-sustaining layer for power devices. Microelectron J, 1998, 29(12): 1005 doi: 10.1016/S0026-2692(98)00065-2
[6]
Coe D J. High voltage semiconductor device. USA Patent, US4754310, 1988
[7]
Tihanyi J. Power MOSFET. USA Patent, US5438215, 1995
[8]
Fujihira T. Theory of semiconductor superjunction devices. Jpn J Appl Phys, 1997, 36(10): 6254
[9]
Deboy G, Marz M, Stengl J P, et al. A new generation of high voltage MOSFETs breaks the limit line of silicon. IEEE International Electron Devices Meeting (IEDM), 1998: 683
[10]
Lorenz L, Deboy G, Knapp A, et al. CooLMOSTM: a new milestone in high voltage power MOS. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 1999: 3
[11]
Zhang W T, Zhang B. Theory of superjunction with NFD and FD modes based on normalized breakdown voltage. IEEE Trans Electron Devices, 2015, 62(12): 4114 doi: 10.1109/TED.2015.2491360
[12]
Kawashima Y, Inomata H, Murakawa K, et al. Narrow-pitch n-channel superjunction UMOSFET for 40–60 V automotive application. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010: 329
[13]
Yamauchi S, Shibata T, Nogami S, et al. 200 V super junction MOSFET fabricated by high aspect ratio trench filling. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2006: 1
[14]
Saito W, Omura I, Aida S, et al. A 15.5 mΩ·cm2 680 V superjunction MOSFET reduced on-resistance by lateral pitch narrowing. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2006: 1
[15]
Sakakibara J, Noda Y, Shibata T, et al. 600 V-class super junction MOSFET with high aspect ratio P/N columns structure. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2008: 299
[16]
Rutter P, Peake S T. Low voltage trenchMOS combining low specific RDS (on) and QG FOM. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010: 325
[17]
Okubo H, Kobayashi K, Kawashima Y. Ultralow on-resistance 30–40 V UMOSFET by 2-D scaling of ion-implanted superjunction structure. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2013: 87
[18]
Miura Y, Ninomiya H, Kobayashi K. High performance superjunction UMOSFETs with split P-columns fabricated by multi-ion-implantations. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2005: 39
[19]
Ninomiya H, Miura Y, Kobayashi K. Ultra-low on-resistance 60–100 V superjunction UMOSFETs fabricated by multiple ion-implantation. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 177
[20]
Dalen R, Rochefort C. Electrical characterisation of vertical vapor phase doped (VPD) RESURF MOSFETs. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 451
[21]
Dalen R, Rochefort C. Vertical multi-RESURF MOSFETs exhibiting record low specific resistance. IEEE International Electron Devices Meeting (IEDM), 2003: 31.1.1
[22]
Rochefort C, Dalen R. Vertical RESURF diodes manufactured by deep-trench etch and vapor-phase doping. IEEE Electron Device Lett, 2004, 25(2): 73 doi: 10.1109/LED.2003.822649
[23]
Hu C M. Optimum doping profile for minimum ohmic resistance and high-breakdown voltage. IEEE Trans Electron Devices, 1979, 26(3): 243 doi: 10.1109/T-ED.1979.19416
[24]
Gan K P, Yang X, Liang Y C, et al. A simple technology for superjunction device fabrication: polyflanked VDMOSFET. IEEE Electron Device Letters, 2002, 23(10): 627 doi: 10.1109/LED.2002.803770
[25]
Hattori Y, Nakashima K, Kuwahara M, et al. Design of a 200 V super junction MOSFET with n-buffer regions and its fabrication by trench filling. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 189
[26]
Kurosaki T, Shishido H, Kitada M, et al. 200 V multi RESURF trench MOSFET (MR-TMOS). IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2003: 211
[27]
Nitta T, Minato T, Yano M, et al. Experimental results and simulation analysis of 250 V super trench power MOSFET (STM). IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2000: 77
[28]
Rochefort C, Dalen R. A scalable trench etch based process for high voltage vertical RESURF MOSFETs. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2005: 35
[29]
Iwamoto S, Takahashi K, Kuribayashi H, et al. Above 500 V class superjunction MOSFETs fabricated by deep trench etching and epitaxial growth. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2005: 31
[30]
Rüb M, Bär M, Deboy G, et al. 550 V superjunction 3.9 Ω·mm2 transistor formed by 25 MeV masked boron implantation. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 455
[31]
Lee SC, Oh K H, Kim S S, et al. 650 V superjunction MOSFET using universal charge balance concept through drift region. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2014: 83
[32]
Onishi Y, Iwamoto S, Sato T, et al. 24 mΩ·cm2 680 V silicon superjunction MOSFET. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2002: 241
[33]
Saito W, Omura L, Aida S, et al. A 20 mΩ·cm2 600 V-class superjunction MOSFET. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 459
[34]
Takahashi K, Kuribayashi H, Kawashima T, et al. 20 mΩ·cm2 660 V super junction MOSFETs fabricated by deep trench etching and epitaxial growth. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2006: 1
[35]
Moens P, Bogman F, Ziad H, et al. UltiMOS: a local charge-balanced trench-based 600 V super-junction device. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2011: 304
[36]
Sugi A, Takei M, Takahashi K, et al. Super junction MOSFETs above 600 V with parallel gate structure fabricated by deep trench etching and epitaxial growth. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2008: 165
[37]
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    Received: 21 September 2017 Revised: 01 November 2017 Online: Accepted Manuscript: 12 December 2017Uncorrected proof: 24 January 2018Published: 02 February 2018

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      Bo Zhang, Wentong Zhang, Ming Qiao, Zhenya Zhan, Zhaoji Li. Concept and design of super junction devices[J]. Journal of Semiconductors, 2018, 39(2): 021001. doi: 10.1088/1674-4926/39/2/021001 B Zhang, W T Zhang, M Qiao, Z Y Zhan, Z J Li. Concept and design of super junction devices[J]. J. Semicond., 2018, 39(2): 021001. doi: 10.1088/1674-4926/39/2/021001.Export: BibTex EndNote
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      Bo Zhang, Wentong Zhang, Ming Qiao, Zhenya Zhan, Zhaoji Li. Concept and design of super junction devices[J]. Journal of Semiconductors, 2018, 39(2): 021001. doi: 10.1088/1674-4926/39/2/021001

      B Zhang, W T Zhang, M Qiao, Z Y Zhan, Z J Li. Concept and design of super junction devices[J]. J. Semicond., 2018, 39(2): 021001. doi: 10.1088/1674-4926/39/2/021001.
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      Concept and design of super junction devices

      doi: 10.1088/1674-4926/39/2/021001
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      • Corresponding author: Email: zhangbo@uestc.edu.cn
      • Received Date: 2017-09-21
      • Revised Date: 2017-11-01
      • Published Date: 2018-02-01

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