J. Semicond. > Volume 37 > Issue 5 > Article Number: 054006

An LDMOS with large SOA and low specific on-resistance

Wenfang Du , Xinjiang Lyu and Xingbi Chen ,

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Abstract: An LDMOS with nearly rectangular-shape safe operation area (SOA) and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be lowered down to 74.7 mΩ·cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ionization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large VGS is obtained and snap-back is suppressed as well.

Key words: LDMOSsafe operation area (SOA)snap-backsplit gate

Abstract: An LDMOS with nearly rectangular-shape safe operation area (SOA) and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be lowered down to 74.7 mΩ·cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ionization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large VGS is obtained and snap-back is suppressed as well.

Key words: LDMOSsafe operation area (SOA)snap-backsplit gate



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Ludikhuize A W. Review of RESURF technology[J]. Proc IEEE ISPSD, 2000: 11.

[2]

[2] Yang F J, Gong J, Su R Y, et. al. 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA[J]. IEEE Trans Electron Devices, 2013, 60: 2847.

[3]

Lyu X, Chen X. An ultralow specific ON-resistance LDMOST using charge balance by split p-gate and n-drift regions[J]. IEEE Trans Electron Devices, 2013, 60: 3821.

[4]

Du W, Lyu X, Ng W T. An ultra-low specific on-resistance LDMOST with self-driven split gate[J]. IEEE Trans Electron Devices, 2015, 62: 1230.

[5]

Hower P L. Safe operating area - a new frontier in LDMOS design[J]. Proc IEEE ISPSD, 2002: 1.

[6]

Parthasarathy V, Khemka V, Zhu R. SOA improvement by a double RESURF LDMOS technique in a power IC technology[J]. Proc IEEE IEDM, 2000: 75.

[7]

Ochoa A, Sexton F W, Wrobel T F. Snap-back: a stable regenerative breakdown mode of MOS devices[J]. IEEE Trans Nucl Sci, 1983, 30: 4127.

[8]

Hower P, Lin J, Pendharka S. A rugged LDMOS for LBC5 technology[J]. Proc IEEE ISPSD, 2005: 327.

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Chen X B. Lateral high-voltage semiconductor devices with majorities of both types for conduction[J]. U.S. Paten.

[10]

Reggiani S, Baccarani G, Gnani E. Explanation of the rugged LDMOS behavior by means of numerical analysis[J]. IEEE Trans Electron Devices, 2009, 56(11): 2811.

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Ludikhuize A W. A review of RESURF technology[J]. Proc IEEE ISPSD, 2000: 11.

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Disney D R, Paul A K, Darwish M. A new 800 V lateral MOSFET with dual conduction paths[J]. Proc IEEE ISPSD, 2001: 399.

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Yang F J, Gong J, Su R Y. A 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA[J]. IEEE Trans Electron Devices, 2013, 60: 2847.

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Su R Y, Yang F J, Tsay J L. State-of-the-art device in high voltage power ICs with lowest on-state resistance[J]. IEDM, 2010.

[15]

Hu C. Optimum doping profile for minimum ohmic resistance and high-breakdown voltage[J]. IEEE Trans Electron Devices, 1979, 26: 243.

[16]

Bidin N, Razak S N A. Crystallization of poly-silicon film by different annealing techniques[J]. Proc IEEE SIECPC, 2011: 1.

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W F Du, X Lyu, X B Chen. An LDMOS with large SOA and low specific on-resistance[J]. J. Semicond., 2016, 37(5): 054006. doi: 10.1088/1674-4926/37/5/054006.

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Manuscript received: 07 September 2015 Manuscript revised: Online: Published: 01 May 2016

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