J. Semicond. > 2022, Volume 43 > Issue 3 > 031401, doi: 10.1088/1674-4926/43/3/031401
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REVIEWS

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Zhiting Lin, Zhongzhen Tong, Jin Zhang, Fangming Wang, Tian Xu, Yue Zhao, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao and Junning Chen

+ Author Affiliations

 Corresponding author: Xiulong Wu, xiulong@ahu.edu.cn

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Abstract: Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

Key words: static random-access memory (SRAM), artificial intelligence (AI), von Neumann bottleneck, computing in-memory (CIM), convolutional neural network (CNN)



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Fig. 1.  (Color online) Overall framework of static random-access memory (SRAM)-based computing in-memory (CIM) for the review: (a) various functions implemented in CIM, (b) operation functions realizable with CIM, and (c) application scenarios of CIM.

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Fig. 2.  (Color online) (a) Standard 6T SRAM cell, (b) dual-Split 6T SRAM cell, and (c) 4+2T SRAM cell.

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Fig. 3.  (Color online) SRAM cells with separated read and write: (a) standard 8T SRAM bit-cell, (b) 7T SRAM cell, (c) 9T SRAM cell, and (d) 10T SRAM cell.

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Fig. 4.  (Color online) SRAM cells based on capacitive coupling: (a) C3SRAM bitcell and (b) M-BC bitcell.

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Fig. 5.  (Color online) (a) Transposable bitcell contains two pairs of access transistors and (b) separated read–write transposable bit cell. (c) Schematic of the transposable 10T bit bitcell.

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Fig. 6.  (Color online) Compact coupling structure: (a) 12T cell and (b) two-way transpose multibitcell.

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Fig. 7.  (Color online) (a) Asymmetric differential sense amplifier (SA), (b) flash ADC, and (c) successive approximation ADC.

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Fig. 8.  (Color online) (a) Weighted array with different capacitor sizes and (b) multi-period weighting technique using capacitors of the same size.

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Fig. 9.  (Color online) Schematic of the column-wise GBL_DAC circuit: (a) Circuit of the constant current source, (b) two-stage MUX, and (c) waveform of the column-wise GBL_DAC circuit. (d) Schematic and waveform of the pulse height modulation circuit.

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Fig. 10.  (Color online) Redundant reference column technology.

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Fig. 11.  (Color online) (a) In-/near-memory computing peripherals and (b) a bit-tree adder.

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Fig. 12.  (Color online) Signed 4-b × 8-b least significant bit (LSB) multiplier: (a) timing diagram and (b) circuit schematic.

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Fig. 13.  (Color online) Boolean operation: (a) Boolean logical operations using an SRAM array, (b) histogram of AND and NOR operation voltages, and (c) schematic of the 8T-SRAM for implementing the IMP and XOR operations.

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Fig. 14.  (Color online) Column-wise BCAM: (a) search example in 3D-CAM and (b) 4+2T. Row-wise TCAM: (c) organization based on 10T and (d) organization based on 6T.

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Fig. 15.  (Color online) Schematic and truth table of the binary dot product: (a) 6T-SRAM binary dot product and (b) 8T-SRAM binary dot product. (c) Ternary dot product: operation of ternary multiplication and XNOR value mapping table.

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Fig. 16.  (Color online) Row of 9T SRAM cells for calculating the Hamming distance.

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Fig. 17.  (Color online) (a) Precharge weighting technology, (b) pulse width weighting, (c) pulse height weighting, and (d) pulse number weighting.

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Fig. 18.  (Color online) (a) 8T-SRAM memory array for computing dot products with 4-bit weight precision and (b) Twin-8T cell.

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Fig. 19.  (Color online) (a) Schematic of SAD circuit and (b) sequence diagram.

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Fig. 20.  (Color online) Implementation of (a) CNN and (b) AES on multiple SRAM arrays.

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Fig. 21.  (Color online) Application in the k-NN algorithm.

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Fig. 22.  (Color online) Application in classifier algorithms.

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Fig. 23.  (Color online) Read disturb issue.

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Fig. 24.  (Color online) (a) Single row activation during normal SRAM read operation, (b) multirow read and nonlinearity during CIM, and (c) inconsistent CIM calculation.

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Fig. 25.  (Color online) Approach of mapping from the common operator set to the actual circuits.

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Fig. 26.  (Color online) Architecture of the bidirectional CIM system, including a reusable and reconfigurable module.

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Fig. 27.  (Color online) Multithreaded CIM macro based on a pipeline processor.

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Table 1.   Static random-access memory (SRAM) bitcells in CIM.

ParameterStructure of the 6T cellCell structure with additional devices
Standard 6TDual-split 6T4+2TRead and write separatingCapacitive couplingTransposableCompact coupling
Ref.
[19]		Refs.
[1, 2]		Ref.
[20]		Ref.
[18]		Ref.
[67]		Ref.
[57]		Refs.
[31, 58]		Refs.
[59, 60, 61]		Refs.
[12, 13]		Refs.
[14, 55]		Ref.
[11]		Ref.
[17]		Ref.
[43]
Cell type6T6T6T8T9T10T8T1C10T1C8T8T10T12TTWT-MC
Process technology28-nm FDSOI65 nm55-nm DDC45 nm65 nm28 nm65 nm65 nm28 nm7 nm28 nm65 nm28 nm
Added circuitNoNoTwo read
ports		One read
port		One read
port		Two read
ports		Two transistors
one cap		Four transistors
one cap		Two read
ports		One read
port		Two read
ports		Pull-up/
down
circuits		Multiply
cell
Read write disturbYesYesNoNoNoNoNoNoNoNoNoNoYes
Area efficiencyHighHighHighMed.Med.Med.LowLowMed.HighLowLowLow
TOPS/mm2NA33.13NANANA17020.20.627.3NANA5.461NA
TOPS/WNA30.49–
55.8
1/1/5b1		41.4
1/1/1b1		NANA1002
1/1/1b1		671.5
1/1/5b1		192–
400
1–8b		0.56/5.27
Arbitrary		6.02
8/1/
11b1		66.7
1/1/1b1		403
1/1/
3.46b1		7.2–61.1
2,4,8/4,
8/10,12,
16,20b1
1Input precesion/Weight precesion/Output precesion. TWT-MC: Two-way transpose multibit accumulation; DDC: deeply depleted channel; FDSOI: full depleted silicon on insulator
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Table 2.   Summary of chip parameters and performance of in-memory Boolean logic and CAM

ParameterRef. [19]Ref. [28]Ref. [20]Ref. [29]Ref. [5]Ref. [68]Ref. [11]
Technology28-nm
FDSOI		180 nm55-nm
DDC		28-nm
FDSOI		65 nm28 nm28 nm
Cell type6T8T4+2T6T8T14T10T
Array size64×648×8128×128128×64128×1281024×32064×64
Supply voltage (V)11.20.80.91.20.90.9
CAMFreq.
(MHz)		370 (1 V)NA270 (0.8 V)1560 (0.9 V)
8.90 (0.38 V)		813
(1.2 V)		1330
(0.9 V)		262 (0.9 V)256 (0.9 V)
Energy
(fJ/bit)		0.6
(1 V)		NA0.45
(0.8 V)		0.13 (0.9 V)0.85
(1.2 V)		0.422
(0.9 V)		1.025 (0.9 V)1.02 (0.9 V)
0.635 (0.7 V)0.632 (0.7 V)
LogicFreq.
(MHz)		NANA230 (0.8 V)NA793 (1.2 V)NA~300(0.9 V)
Energy
(fJ/bit)		NANA24.1 (0.8 V)NA~31 (1.2 V)NA~15 (0.9 V)
~22.5 (1 V)~12.5 (0.8 V)
16.6 (0.8 V)~10.5 (0.7 V)
Search mode11221212
FunctionSRAM/
CAM/Logic		SRAM/ TCAM/ Left Shift/ Right/ShiftSRAM/
CAM/Logic		BCAM/SRAM/
Pseudo-TCAM		SRAM/
CAM/
Logic		SRAM/
TCAM		SRAM/CAM/
Logic/Matrix transpose
1Row-wise search. 2Column-wise search. DDC, deeply depleted channel; FDSOI, full depleted silicon on insulator.
DownLoad: CSV

Table 3.   Summary of chip parameters and performance of single- and multibit operations.

ParameterRefs. [1, 2]Ref. [10]Refs. [15, 16]Ref. [32]Ref. [31]Ref. [44]Ref. [33]Refs. [24, 37]Ref. [34]
Tchnology65-nm CMOS65-nm CMOS130-nm CMOS55-nm CMOS65-nm CMOS65-nm TSMC55-nm CMOS7-nm FinFET65nm
Cell structureDCS 6T10T6TTwin-8T8T1C6T6T8T6T
Array size 4 Kb16 Kb16 Kb64×60 b2 KB64 Kb4 Kb4 Kb64 Kb
Chip area (μm2)NA6.3×1042.67×1054.69×1048.1×104NA5.94×1063.2×1031.75×105
Input precision (bit)1651, 2, 4151, 2, 7, 844
Weight precision (bit)1112, 5151, 2, 841, 2, 3
4, 5, 8
Output precision (bit)16NA3, 5, 75NA3, 7, 10, 194NA
Computing mechanismAnalogDigital+
Analog		Digital+
Analog		AnalogAnalogAnalogDigital+
Analog		AnalogAnalog
ModelXNORNN/MBNNCNNClassifyCNNCNNVGG
LeNet-5		CNNVGG-9 NNCNN
Energy efficiency
(TOPS/W)		30.49–55.840.3 (1 V)
51.3 (0.8 V)		NA18.37–
72.03		671.5NA0.6–40.2351
(0.8 V)		49.4
(Input:
4b Weight:1b)
Throughput (GOPS)278.28 (1 V)
1 (0.4 V)		NA21.2~
67.5		1638NA5.14-329.14372.4(0.8 V)573.4
(Input:
4b Weight:2b)
Accu-racyMNIST96.5%
(XNORNN)
95.1%
(MBNN)		98%(0.8 V)
98.3%(1 V)		90%90.02%–
99.52%		98.30%99%98.56%–
99.59%		98.51%–
99.99%		98.80%
CIFAR 10NANANA85.56%~
90.42%		85.50%88.83%85.97%-91.93%22.89%-96.76%89.00%
DownLoad: CSV
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    Received: 28 August 2021 Revised: 04 November 2021 Online: Accepted Manuscript: 27 December 2021Uncorrected proof: 31 December 2021Published: 10 March 2022

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      Article Navigation >  Journal of Semiconductors  > 2022  >  43(3): 031401
      Zhiting Lin, Zhongzhen Tong, Jin Zhang, Fangming Wang, Tian Xu, Yue Zhao, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Junning Chen. A review on SRAM-based computing in-memory: Circuits, functions, and applications[J]. Journal of Semiconductors, 2022, 43(3): 031401. doi: 10.1088/1674-4926/43/3/031401 Z T Lin, Z Z Tong, J Zhang, F M Wang, T Xu, Y Zhao, X L Wu, C Y Peng, W J Lu, Q Zhao, J N Chen, A review on SRAM-based computing in-memory: Circuits, functions, and applications[J]. J. Semicond., 2022, 43(3): 031401. doi: 10.1088/1674-4926/43/3/031401.Export: BibTex EndNote
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      Zhiting Lin, Zhongzhen Tong, Jin Zhang, Fangming Wang, Tian Xu, Yue Zhao, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Junning Chen. A review on SRAM-based computing in-memory: Circuits, functions, and applications[J]. Journal of Semiconductors, 2022, 43(3): 031401. doi: 10.1088/1674-4926/43/3/031401

      Z T Lin, Z Z Tong, J Zhang, F M Wang, T Xu, Y Zhao, X L Wu, C Y Peng, W J Lu, Q Zhao, J N Chen, A review on SRAM-based computing in-memory: Circuits, functions, and applications[J]. J. Semicond., 2022, 43(3): 031401. doi: 10.1088/1674-4926/43/3/031401.
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      A review on SRAM-based computing in-memory: Circuits, functions, and applications

      doi: 10.1088/1674-4926/43/3/031401

      • School of Integrated Circuits, Anhui University, Hefei 230601, China

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      • Author Bio:

        Zhiting Lin (SM’16) received the B.S. and Ph.D. degrees in electronics and information engineering from the University of Science and Technology of China (USTC), Hefei, China, in 2004 and 2009, respectively. From 2015 to 2016, he was a visiting scholar with the Engineering and Computer Science Department, Baylor University, Waco, TX, USA. In 2011, he joined the Department of Electronics and Information Engineering, Anhui University, Hefei, Anhui. He is currently a professor at the Department of Integrated Circuit, Anhui University. He has published about 50 articles and holds over 20 Chinese patents. His research interests include pipeline analog-to-digital converters and high-performance static random-access memory

        Xiulong Wu received the B.S. degree in computer science from the University of Science and Technology of China (USTC), Hefei, China, in 2001, and the M.S. and Ph.D. degrees in electronic engineering from Anhui University, Hefei, in 2005 and 2008, respectively. From 2013 to 2014, he was a visiting scholar with the Engineering Department, The University of Texas at Dallas, Richardson, TX, USA. He is a professor at Anhui University. He has published about 60 articles and holds over 10 Chinese patents. His research interests include high-performance static random-access memory and mixed-signal ICs

      • Corresponding author: xiulong@ahu.edu.cn
      • Received Date: 2021-08-28
      • Accepted Date: 2021-12-23
      • Revised Date: 2021-11-04
      • Published Date: 2022-03-10

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