Fig. 1.
(Color online) (a) 3-D and (b) 2-D view of the proposed asymmetric dual-k SiC S/D FinFET structure in TCAD structure editor.
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Maisagalla Gopal, Atul Awadhiya, Nandakishor Yadav, S. K. Vishvakarma, Vaibhav Neema. Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET[J]. Journal of Semiconductors, 2018, 39(10): 104001. doi: 10.1088/1674-4926/39/10/104001
M Gopal, A Awadhiya, N Yadav, S K Vishvakarma, V Neema, Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET[J]. J. Semicond., 2018, 39(10): 104001. doi: 10.1088/1674-4926/39/10/104001.
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Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET
doi: 10.1088/1674-4926/39/10/104001
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Abstract
We propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a stressor for a Si channel. This enhances the device performance in terms of electron mobility (eMobility), current driving capabilities, transconductance (Gm) and subthreshold slope (SS). The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance. We analysed the variation in drive current for different values of carbon (C) mole fraction y in Si1−yCy. It is found that the mole fraction also helps to improve device lifetime, performance enhancement also pointed by transconductance variation with the gate length. All the simulations are performed in the 3-D Sentaurus TCAD tool. The proposed device structure achieved ION = 2.17 mA/μm for Si0.3C0.7 and found that Si0.5C0.5 is more suitable for the perspective of a process variation effect for 14 nm as the gate length. We introduce reliability issues and their solutions for Si1−yCy FinFET for the first time. -
References
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