J. Semicond. > Volume 37 > Issue 5 > Article Number: 055005

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

Xuemin Li , Mao Ye , , Gongyuan Zhao , Yun Zhang and Yiqiang Zhao

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Abstract: A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/℃ without trimming, over a temperature range from -40 to 120 ℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2.

Key words: voltage referencesub-referencecurvature compensationsubthreshold

Abstract: A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/℃ without trimming, over a temperature range from -40 to 120 ℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2.

Key words: voltage referencesub-referencecurvature compensationsubthreshold



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Geng Junfeng, Zhao Yiqiang, Zhao Hongliang. A high order curvature corrected CMOS bandgap voltage reference with constant current technique[J]. International Journal of Circuit Theory and Applications, 2012, 42(1): 43.

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Osaki Y, Hirose T, Kuroki N. 1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs[J]. IEEE J Solid-State Circuits, 2013, 48(6): 1530.

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Shrivastava A, Craig K, Roberts N E. A 32 nW bandgap reference voltage operational from 0.5 V supply for ultra-low power systems[J]. IEEE ISSCC Dig Tech Papers, 2015: 94.

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Magnelli L, Crupi F, Corsonello P. A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference[J]. IEEE J Solid-State Circuits, 2011, 46(2): 465.

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Leung K N, Mok P. A CMOS voltage reference based on weighted Δ VGS for CMOS low-dropout linear regulators[J]. IEEE J Solid-State Circuits, 2003, 38(1): 146.

[13]

Zhuang H, Zhu Z, Yang Y. A 19-nW 0.7-V CMOS voltage reference with no amplifiers and no clock circuit[J]. IEEE Trans Circuits Syst II, 2014, 61(11): 830.

[14]

Yang Y, Binkley D M, Li L. All-CMOS sub bandgap reference circuit operating at low supply voltage[J]. Proc IEEE Int Symp Circuits Syst, 2011: 893.

[15]

Zhou Z, Zhu P, Shi Y. A CMOS voltage reference based on mutual compensation of Vtn and Vtp[J]. IEEE Trans Circuits Syst II, 2012, 59(6): 341.

[16]

Seok M, Kim G, Blaauw D. A portable 2-transistor pico watt temperature-compensated voltage reference operating at 0.5 V.[J]. IEEE J Solid-State Circuits, 2012, 47(1): 2534.

[17]

Filanovsky I M, Allam A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits[J]. IEEE Trans Circuits Syst I, 2001, 48(7): 876.

[18]

Duan Q, Roh J. A 1.2-V 4.2-ppm/℃ high-order curvature-compensated CMOS bandgap reference[J]. IEEE Trans Circuits Syst I, 2015, 62(3): 662.

[19]

Kok C W, Tam W S. CMOS voltage references: an analytical and practical perspective[J]. John Wiley & Sons, 2013.

[20]

Ueno K, Hirose T, Asai T. A 1-μ W 600-ppm/℃ current reference circuit consisting of subthreshold CMOS circuits[J]. IEEE Trans Circuits Syst II, 2010, 57(9): 681.

[21]

Ceekala V G, Lewicki L D, Wieser J B. A method for reducing the effects of random mismatches in CMOS bandgap references[J]. IEEE ISSCC Dig Tech Papers, 2002: 318.

[22]

Hastings A. The art of analog layout[J]. Englewood Cliffs, Prentice-Hall, 2005.

[23]

Ge G, Zhang C, Hoogzaad G. A single-trim CMOS bandgap reference with a inaccuracy of 0.15% from 40 ℃ to 125 ℃[J]. IEEE J Solid-State Circuits, 2011, 46(11): 2693.

[24]

Ker M D Chen J S, Chu C Y. New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation[J]. IEEE Trans Circuits Syst II, 2006, 53(8): 667.

[1]

Rincon-Mora G. Voltage reference-from diodes to precision high-order bandgap circuits[J]. Wiley-IEEE Press, 2001.

[2]

Song B, Gray P. A precision curvature-compensated CMOS bandgap reference[J]. IEEE J Solid-State Circuits, 1983, SC-18(6): 634.

[3]

Lee I, Kim G, Kim W. Exponential curvature-compensated BiCMOS bandgap references[J]. IEEE J Solid-State Circuits, 1994, 29(11): 1396.

[4]

Rincon-Mora G, Allen P. 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference[J]. IEEE J Solid-State Circuits, 1998, 33(10): 1551.

[5]

Leung K N, Mok P K, Leung C Y. 2-V 23 μA 5.3 ppm/℃ curvature-compensated CMOS bang-gap reference[J]. IEEE J Solid-State Circuits, 2003, 38(3): 561.

[6]

Geng Junfeng, Zhao Yiqiang, Zhao Hongliang. A high order curvature corrected CMOS bandgap voltage reference with constant current technique[J]. International Journal of Circuit Theory and Applications, 2012, 42(1): 43.

[7]

Osaki Y, Hirose T, Kuroki N. 1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs[J]. IEEE J Solid-State Circuits, 2013, 48(6): 1530.

[8]

Lee K K, Lande T S, Hafliger P D. A sub-μW bandgap reference circuit with an inherent curvature-compensation property[J]. IEEE Trans Circuits Syst I, 2015, 62(1): 1.

[9]

Shrivastava A, Craig K, Roberts N E. A 32 nW bandgap reference voltage operational from 0.5 V supply for ultra-low power systems[J]. IEEE ISSCC Dig Tech Papers, 2015: 94.

[10]

De Vita Giannaccone G. A sub-1-V, 10 ppm/℃, nanopowervoltage reference generator[J]. IEEE J Solid-State Circuits, 2007, 42(7): 1536.

[11]

Magnelli L, Crupi F, Corsonello P. A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference[J]. IEEE J Solid-State Circuits, 2011, 46(2): 465.

[12]

Leung K N, Mok P. A CMOS voltage reference based on weighted Δ VGS for CMOS low-dropout linear regulators[J]. IEEE J Solid-State Circuits, 2003, 38(1): 146.

[13]

Zhuang H, Zhu Z, Yang Y. A 19-nW 0.7-V CMOS voltage reference with no amplifiers and no clock circuit[J]. IEEE Trans Circuits Syst II, 2014, 61(11): 830.

[14]

Yang Y, Binkley D M, Li L. All-CMOS sub bandgap reference circuit operating at low supply voltage[J]. Proc IEEE Int Symp Circuits Syst, 2011: 893.

[15]

Zhou Z, Zhu P, Shi Y. A CMOS voltage reference based on mutual compensation of Vtn and Vtp[J]. IEEE Trans Circuits Syst II, 2012, 59(6): 341.

[16]

Seok M, Kim G, Blaauw D. A portable 2-transistor pico watt temperature-compensated voltage reference operating at 0.5 V.[J]. IEEE J Solid-State Circuits, 2012, 47(1): 2534.

[17]

Filanovsky I M, Allam A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits[J]. IEEE Trans Circuits Syst I, 2001, 48(7): 876.

[18]

Duan Q, Roh J. A 1.2-V 4.2-ppm/℃ high-order curvature-compensated CMOS bandgap reference[J]. IEEE Trans Circuits Syst I, 2015, 62(3): 662.

[19]

Kok C W, Tam W S. CMOS voltage references: an analytical and practical perspective[J]. John Wiley & Sons, 2013.

[20]

Ueno K, Hirose T, Asai T. A 1-μ W 600-ppm/℃ current reference circuit consisting of subthreshold CMOS circuits[J]. IEEE Trans Circuits Syst II, 2010, 57(9): 681.

[21]

Ceekala V G, Lewicki L D, Wieser J B. A method for reducing the effects of random mismatches in CMOS bandgap references[J]. IEEE ISSCC Dig Tech Papers, 2002: 318.

[22]

Hastings A. The art of analog layout[J]. Englewood Cliffs, Prentice-Hall, 2005.

[23]

Ge G, Zhang C, Hoogzaad G. A single-trim CMOS bandgap reference with a inaccuracy of 0.15% from 40 ℃ to 125 ℃[J]. IEEE J Solid-State Circuits, 2011, 46(11): 2693.

[24]

Ker M D Chen J S, Chu C Y. New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation[J]. IEEE Trans Circuits Syst II, 2006, 53(8): 667.

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X M Li, M Ye, G Y Zhao, Y Zhang, Y Q Zhao. A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE[J]. J. Semicond., 2016, 37(5): 055005. doi: 10.1088/1674-4926/37/5/055005.

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Manuscript received: 25 August 2015 Manuscript revised: Online: Published: 01 May 2016

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