Journal of Semiconductors>>2017,Volume 38>>Issue 12:124001-5    < Previous Article | Next Article >  
S Chakraborty, A Dasgupta, R Das, M Kar, A Kundu and C K Sarkar.Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach[J].Journal of Semiconductors,2017,38(12):124001-5
Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach
Abstract: In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET.
Keywords: 14 nm  double gate MOSFET  look-up table  VerilogA
Author NameAffiliation
S Chakraborty Department of Electronics and Communications Engineering Heritage Institute of Technology, Kolkata 700107, India 
A Dasgupta Department of Electronics and Communications Engineering Heritage Institute of Technology, Kolkata 700107, India 
R Das Department of Electronics and Communications Engineering Heritage Institute of Technology, Kolkata 700107, India 
M Kar Department of Electronics and Communications Engineering Heritage Institute of Technology, Kolkata 700107, India 
A Kundu Department of Electronics and Communications Engineering Heritage Institute of Technology, Kolkata 700107, India 
C K Sarkar Nano Device Simulation Laboratory, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India 
 
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