| Citation: |
Gao Zhuo, Yang Yi, Zhong Shiqiang, Yang Xu, Huang Lingyi, Hu Weiwu. A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J]. Journal of Semiconductors, 2009, 30(1): 015004. doi: 10.1088/1674-4926/30/1/015004
Gao Z, Yang Y, Zhong S Q, Yang X, Huang L Y, Hu W W. A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J]. J. Semicond., 2009, 30(1): 015004. doi: 10.1088/1674-4926/30/1/015004.
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A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS
doi: 10.1088/1674-4926/30/1/015004
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Abstract
This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186 μm2 and consumes 5.3 mW power.-
Keywords:
- serial link,
- PAM,
- equalizer,
- pre-emphasis,
- CTLE
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References
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Proportional views
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