SEMICONDUCTOR INTEGRATED CIRCUITS

An 11 mW 79 dB DR ΔΣ modulator for ADSL applications

Zhu Yingjia, Liu Liyuan and Li Dongmei

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Abstract: This paper shows the design of a second-order multi-bit △Σ modulator with hybrid structure for ADSL applications. A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12% of the time from PH1, which relaxes the speed of OTAs, comparators and the DEMblock. The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder. The chip is designed and fabricated in UMC 0.18 μm CMOS technology. Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz, the modulator can achieve 79 dB dynamic range, 71.3 dB SNDR, 11 mW power consumption from a 1.8 V power supply. The FOM is 1.47 pJ/step.

Key words: ?Σ modulator

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    Received: 18 August 2015 Revised: 11 June 2009 Online: Published: 01 October 2009

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      Zhu Yingjia, Liu Liyuan, Li Dongmei. An 11 mW 79 dB DR ΔΣ modulator for ADSL applications[J]. Journal of Semiconductors, 2009, 30(10): 105003. doi: 10.1088/1674-4926/30/10/105003 Zhu Y J, Liu L Y, Li D M. An 11 mW 79 dB DR △Σ modulator for ADSL applications[J]. J. Semicond., 2009, 30(10): 105003. doi:  10.1088/1674-4926/30/10/105003.Export: BibTex EndNote
      Citation:
      Zhu Yingjia, Liu Liyuan, Li Dongmei. An 11 mW 79 dB DR ΔΣ modulator for ADSL applications[J]. Journal of Semiconductors, 2009, 30(10): 105003. doi: 10.1088/1674-4926/30/10/105003

      Zhu Y J, Liu L Y, Li D M. An 11 mW 79 dB DR △Σ modulator for ADSL applications[J]. J. Semicond., 2009, 30(10): 105003. doi:  10.1088/1674-4926/30/10/105003.
      Export: BibTex EndNote

      An 11 mW 79 dB DR ΔΣ modulator for ADSL applications

      doi: 10.1088/1674-4926/30/10/105003
      • Received Date: 2015-08-18
      • Accepted Date: 2009-04-27
      • Revised Date: 2009-06-11
      • Published Date: 2009-09-28

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