| Citation: |
Liu Zhen, Jia Song, Wang Yuan, Ji Lijiu, Zhang Xing. Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit[J]. Journal of Semiconductors, 2009, 30(12): 125013. doi: 10.1088/1674-4926/30/12/125013
Liu Z, Jia S, Wang Y, Ji L J, Zhang X. Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit[J]. J. Semicond., 2009, 30(12): 125013. doi: 10.1088/1674-4926/30/12/125013.
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Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit
doi: 10.1088/1674-4926/30/12/125013
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Abstract
This paper describes an 8-bit 125MHz low-power CMOS fully-folding analog-to-digital converter (ADC). A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5 μm CMOS technology and occupies a die area of 2 × 1.5 mm2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/–0.8 LSB and 0.9 LSB/–1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.-
Keywords:
- analog-to-digital converter
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