Abstract: This paper presents a fully differential dual gain low noise amplifier (DGLNA) for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications. The effect of input parasitics on the inductively degenerated cascode LNA is analyzed. Circuit design details within the guidelines of the analysis are presented. The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process. The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss. In high gain mode, the measured noise figure (NF) is 2.3–3 dB in the whole 2.45-GHz ISM band. The measured 1-dB compression point, IIP3 and IIP2 is –9, 1 and 33 dBm, respectively. The DGLNA consumes 2 mA of current from a 1.8 V power supply.

Key words: CMOS low noise amplifier, input parasitics ,  low power,  noise figure,  ZigBee,  IEEE 802.15.4