Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology

Cao Yuhan; Luo Le

doi:10.1088/1674-4926/30/8/086001

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Cao Yuhan, Luo Le. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. Journal of Semiconductors, 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001 Cao Y H, Luo L. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. J. Semicond., 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001.Export: BibTex EndNote

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Cao Yuhan, Luo Le. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. Journal of Semiconductors, 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001

Cao Y H, Luo L. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. J. Semicond., 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001.

Export: BibTex EndNote

Citation:

Cao Yuhan, Luo Le. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. Journal of Semiconductors, 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001

Cao Y H, Luo L. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. J. Semicond., 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001.

Export: BibTex EndNote

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Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology

doi: 10.1088/1674-4926/30/8/086001

Cao Yuhan,
Luo Le

State Key Laboratories of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
State Key Laboratories of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China

Received Date: 2015-08-18
Accepted Date: 2009-02-17
Revised Date: 2009-04-07
Published Date: 2009-07-31

Abstract

Abstract

A novel wafer level bonding method based on Cu–Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu₆Sn₅ phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10^-9 atm cc/s are possible, meeting the demandsof MIL-STD-883E.
- wafer level package; Cu–Sn isothermal solidification technology; hermeticity

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