| Citation: |
Yuan Ling, Ni Weining, Hao Zhikun, Shi Yin, Li Wenchang. A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC[J]. Journal of Semiconductors, 2009, 30(9): 095003. doi: 10.1088/1674-4926/30/9/095003
Yuan L, Ni W N, Hao Z K, Shi Y, Li W C. A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC[J]. J. Semicond., 2009, 30(9): 095003. doi: 10.1088/1674-4926/30/9/095003.
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A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC
doi: 10.1088/1674-4926/30/9/095003
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Abstract
Abstract: This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35 μm COMS technology with active area of 2.0 × 2.5 mm2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.-
Keywords:
- direct digital frequency synthesizer,
- nonlinear DAC,
- segmented,
- ROM-less,
- CML
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References
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