Abstract: A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented. The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area. Implemented in the 0.18-µm mixed-signal CMOS process, the divider operates over a wide range of 1–7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is –125.3 dBc/Hz at an offset of 100 kHz. The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2. The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.

Key words: frequency divider