| Citation: |
Juang Miin-Horng, Chang Chia-Wei, Shye Der-Chih, Hwang Chuan-Chou, Wang Jih-Liang, Jang Sheng-Liang. A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors[J]. Journal of Semiconductors, 2010, 31(6): 064003. doi: 10.1088/1674-4926/31/6/064003
Juang M H, Chang C W, Shye D C, Hwang C C, Wang J L, Jang S L. A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors[J]. J. Semicond., 2010, 31(6): 064003. doi: 10.1088/1674-4926/31/6/064003.
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A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors
doi: 10.1088/1674-4926/31/6/064003
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Abstract
A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (or boron) dopant through the spacer, and then the nC-source/drain (nC-S/D) (or pC-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single nC-S/D (or pC-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme. As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.-
Keywords:
- polycrystalline-Si thin-film transistor
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