| Citation: |
Liu Yong, Tang Zhaohuan, Wang Zhikuan, Yang Yonghui, Yang Weidong, Hu Yonggui. Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process[J]. Journal of Semiconductors, 2010, 31(8): 084006. doi: 10.1088/1674-4926/31/8/084006
Liu Y, Tang Z H, Wang Z K, Yang Y H, Yang W D, Hu Y G. Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process[J]. J. Semicond., 2010, 31(8): 084006. doi: 10.1088/1674-4926/31/8/084006.
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Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process
doi: 10.1088/1674-4926/31/8/084006
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Abstract
A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC (digital-to-analog converter). With this process, an NJFET with a pinch-off voltage of about –1.5 V and a breakdown voltage of about 16 V, an NLDDMOS (N-type lightly-dosed-drain in MOS) with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V, and a Zener diode with a reverse voltage of about 5.6 V were obtained. Measurement results showed that the converter had a reference temperature coefficient of less than ± 25 ppm/℃, a differential coefficient error of less than ± 0.3 LSB, and a linear error of less than ± 0.5 LSB. The depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or DACs. -
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