| Citation: |
Yang Siyu, Zhang Hui, Fu Wenhui, Yi Ting, Hong Zhiliang. A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator[J]. Journal of Semiconductors, 2011, 32(3): 035002. doi: 10.1088/1674-4926/32/3/035002
Yang S Y, Zhang H, Fu W H, Yi T, Hong Z L. A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator[J]. J. Semicond., 2011, 32(3): 035002. doi: 10.1088/1674-4926/32/3/035002.
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A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator
doi: 10.1088/1674-4926/32/3/035002
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Abstract
A low power 12-bit 200-kS/s SAR ADC is proposed. This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator. The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB, respectively, with a power consumption of 72 μW at a 200-kS/s sampling rate. The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step. -
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