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Regular FPGA based on regular fabric

Chen Xun, Zhu Jianwen and Zhang Minxuan

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Abstract: In the sub-wavelength regime, design for manufacturability (DFM) becomes increasingly important for field programmable gate arrays (FPGAs). In this paper, an automated tile generation flow targeting micro-regular fabric is reported. Using a publicly accessible, well-documented academic FPGA as a case study, we found that compared to the tile generators previously reported, our generated micro-regular tile incurs less than 10% area overhead, which could be potentially recovered by process window optimization, thanks to its superior printability. In addition, we demonstrate that on 45 nm technology, the generated FPGA tile reduces lithography induced process variation by 33%, and reduce probability of failure by 21.2%. If a further overhead of 10% area can be recovered by enhanced resolution, we can achieve the variation reduction of 93.8% and reduce the probability of failure by 16.2%.

Key words: FPGA

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    Received: 18 August 2015 Revised: 12 April 2011 Online: Published: 01 August 2011

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      Chen Xun, Zhu Jianwen, Zhang Minxuan. Regular FPGA based on regular fabric[J]. Journal of Semiconductors, 2011, 32(8): 085015. doi: 10.1088/1674-4926/32/8/085015 Chen X, Zhu J W, Zhang M X. Regular FPGA based on regular fabric[J]. J. Semicond., 2011, 32(8): 085015. doi: 10.1088/1674-4926/32/8/085015.Export: BibTex EndNote
      Citation:
      Chen Xun, Zhu Jianwen, Zhang Minxuan. Regular FPGA based on regular fabric[J]. Journal of Semiconductors, 2011, 32(8): 085015. doi: 10.1088/1674-4926/32/8/085015

      Chen X, Zhu J W, Zhang M X. Regular FPGA based on regular fabric[J]. J. Semicond., 2011, 32(8): 085015. doi: 10.1088/1674-4926/32/8/085015.
      Export: BibTex EndNote

      Regular FPGA based on regular fabric

      doi: 10.1088/1674-4926/32/8/085015
      • Received Date: 2015-08-18
      • Accepted Date: 2011-02-20
      • Revised Date: 2011-04-12
      • Published Date: 2011-07-19

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