| Citation: |
Shao Jianjian, Li Weitao, Sun Cao, Li Fule, Zhang Chun, Wang Zhihua. A digital background calibration algorithm of a pipeline ADC based on output code calculation[J]. Journal of Semiconductors, 2012, 33(11): 115010. doi: 10.1088/1674-4926/33/11/115010
Shao J J, Li W T, Sun C, Li F L, Zhang C, Wang Z H. A digital background calibration algorithm of a pipeline ADC based on output code calculation[J]. J. Semicond., 2012, 33(11): 115010. doi: 10.1088/1674-4926/33/11/115010.
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A digital background calibration algorithm of a pipeline ADC based on output code calculation
doi: 10.1088/1674-4926/33/11/115010
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Abstract
This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter (ADC). The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic. Based on the analysis of the output codes, the calibration logic estimates the bit weight of each stage and corrects the outputs. An experimental 14-bit pipelined ADC is fabricated to verify the algorithm. The results show that INL errors drop from 20 LSB to 1.7 LSB, DNL errors drop from 2 LSB to 0.4 LSB, SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB. The linearity of the pipelined ADC is improved significantly.-
Keywords:
- pipeline
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] -
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