Abstract: A CMOS low-noise amplifier (LNA) operating at 31.7 GHz with a low input return loss (S₁₁) and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to generate more than one S₁₁ dip below -10 dB level. The principle of the matching circuit is analyzed and the critical factors with significant effect on the input impedance (Z_in) are determined. The relationship between the input impedance and the load configuration is explored in depth, which is seldom concentrated upon previously. In addition, the noise of the input stage is modeled using a cascading matrix instead of conventional noise theory. In this way Z_in and the noise figure can be calculated using one uniform formula. The linearity analysis is also performed in this paper. Finally, an LNA was designed for demonstration purposes. The measurement results show that the proposed LNA achieves a maximum power gain of 9.7 dB and an input return loss of < -10 dB from 29 GHz to an elevated frequency limited by the measuring range. The measured input-referred compression point and the third order inter-modulation point are -7.8 and 5.8 dBm, respectively. The LNA is fabricated in a 90-nm RF CMOS process and occupies an area of 755 × 670 μm² including pads. The whole circuit dissipates a DC power of 24 mW from one 1.3-V supply.

Key words: CMOS