SEMICONDUCTOR INTEGRATED CIRCUITS

A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS

Xu Yang, Chi Baoyong, Xu Yang , Qi Nan and Wang Zhihua

+ Author Affiliations

PDF

Abstract: A low-power wideband hybrid automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers (PGAs), a differential peak detector, two comparators, a control algorithm logic, a decoder and the reference voltage source. Besides being controlled by an AGC loop, the gain of PGAs could alternatively be controlled by an off-chip digital baseband processor through the SPI interface. To obtain low power consumption and noise, an improved source degenerated amplifier is adopted, and the I/Q path phase mismatch within the ±5° range is calibrated with 0.2° accuracy. Implemented in 65 nm CMOS, the measured PGA total gains range from 9.8 to 59.5 dB with an average step of 0.95 dB and simulated bandwidth of more than 110 MHz. The settling time is about 180 μ s with 80% AM input with measured signal power from --76.7 to --56.6 dBm from a radio-frequency amplifier (RFA) input port, and also reduces to 90 μs with clock frequency doubling. The single AGC consumes almost 0.8 mA current from the 2.5-V supply and occupies an area of 750 × 300 μm2.

Key words: AGChybridGNSSPGAsI/Q phase calibrationsettling time

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3157 Times PDF downloads: 1715 Times Cited by: 0 Times

    History

    Received: 20 August 2015 Revised: 06 February 2012 Online: Published: 01 July 2012

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Xu Yang, Chi Baoyong, Xu Yang , Qi Nan, Wang Zhihua. A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS[J]. Journal of Semiconductors, 2012, 33(7): 075006. doi: 10.1088/1674-4926/33/7/075006 Xu Yang, Chi B Y, Xu Y, Qi N, Wang Z H. A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS[J]. J. Semicond., 2012, 33(7): 075006. doi: 10.1088/1674-4926/33/7/075006.Export: BibTex EndNote
      Citation:
      Xu Yang, Chi Baoyong, Xu Yang , Qi Nan, Wang Zhihua. A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS[J]. Journal of Semiconductors, 2012, 33(7): 075006. doi: 10.1088/1674-4926/33/7/075006

      Xu Yang, Chi B Y, Xu Y, Qi N, Wang Z H. A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS[J]. J. Semicond., 2012, 33(7): 075006. doi: 10.1088/1674-4926/33/7/075006.
      Export: BibTex EndNote

      A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS

      doi: 10.1088/1674-4926/33/7/075006
      Funds:

      The National Natural Science Foundation of China

      The National High Technology Research and Development Program of China (863 Program)

      The National Science and Technology Major Projects of China

      • Received Date: 2015-08-20
      • Accepted Date: 2012-01-05
      • Revised Date: 2012-02-06
      • Published Date: 2012-06-27

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return