SEMICONDUCTOR INTEGRATED CIRCUITS

A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability

Bin Li, Xiangning Fan, Wei Li, Li Zhang and Zhigong Wang

+ Author Affiliations

 Corresponding author: Fan Xiangning, xnfan@seu.edu.cn

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Abstract: A fully integrated hybrid integer/fractional frequency synthesizer is presented. With a single multi-band voltage-controlled-oscillator (VCO), the frequency synthesizer can support GPS, Galileo, Compass and TD-SCDMA standards. Design is carefully performed to trade off power, die area and phase noise performance. By reconfiguring between the integer mode and fractional mode, different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously. Moreover, a long sequence length, reduced hardware complexity multi-stage-noise-shaping (MASH) Δ-Σ modulator is employed to reduce fractional spur in the fractional mode. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4-16.2 mA from a 1.8 V power supply. The measured phase noise is lower than-80 dBc/Hz at 100 kHz offset and-113 to-124 dBc/Hz at 1 MHz offset respectively, while the measured reference spur is-71 dBc in integer mode and the fractional spur is-65 dBc in fractional mode.

Key words: multi-standardfrequency synthesizerglobal navigation satellite system (GNSS)TD-SCDMAcellular network positioning



[1]
Sand S, Mensing C, Ancha S, et al. Communications and GNSS based navigation:a comparison of current and future trends. Mobile and Wireless Communications Summit, 2007:1 http://ieeexplore.ieee.org/document/4299058/keywords
[2]
Jo J G, Lee J H, Park D J, et al. A L1-band dual-mode RF receiver for GPS and Galileo in 0.18μm CMOS. Radio Frequency Integrated Circuits Symposium, RFIC, 2008:21 https://zh.scribd.com/doc/173018586/Fiber-Optics-Illustrated-Dictionary
[3]
Lu L, Chen J, Yuan L, et al. An 18 mW 1.175-2 GHz frequency synthesizer with constant bandwidth for DVB-T tuners. IEEE Trans Microw Theory Tech, 2009, 57(4):928 doi: 10.1109/TMTT.2009.2014449
[4]
Song J, Park I C. Spur-free MASH delta-Sigma modulation. IEEE Trans Circuits Syst I:Regular Papers, 2010, 57(9):2426 doi: 10.1109/TCSI.2010.2043993
[5]
Yao C Y, Hsieh C C. Hardware simplification to the delta path in a MASH 111 delta sigma modulator. IEEE Trans Circuits Syst Ⅱ:Express Briefs, 2009, 56(4):270 doi: 10.1109/TCSII.2009.2015387
[6]
Hegazi E, Sjoland H, Abidi A A. A filtering technique to lower LC oscillator phase noise. IEEE J Solid-State Circuits, 2001, 36(12):1921 doi: 10.1109/4.972142
[7]
Hegazi E, Abidi A A. Varactor characteristics, oscillator tuning curves, and AM-FM conversion. IEEE J Solid-State Circuits, 2003, 38(6):1033 doi: 10.1109/JSSC.2003.811968
[8]
Mira J, Divel T, Ramet S, et al. Distributed MOS varactor biasing for VCO gain equalization in 0.13μm CMOS technology. Radio Frequency Integrated Circuits Symposium, RFIC, 2004:131 https://zh.scribd.com/document/145600695/RE-1985-11
[9]
Hwang I C, Baek D. A 0.93 mA spur-enhanced frequency synthesizer for L1/L5 dual-band GPS/Galileo RF receiver. IEEE Microw Wireless Compon Lett, 2010, 20(6):355 doi: 10.1109/LMWC.2010.2047533
[10]
Xiao Shimao, Yu Yunfeng, Ma Chengyan, et al. A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver. Journal of Semiconductors, 2010, 31(3):035004 doi: 10.1088/1674-4926/31/3/035004
[11]
Zhou Chunyuan, Li Guoling, Zhang Chun, et al. A fractional-N frequency synthesizer for WCDMA/Bluetooth/ZigBee applications. Journal of Semiconductors, 2009, 30(7):075008 doi: 10.1088/1674-4926/30/7/075008
[12]
Yin Xizhen, Xiao Shimao, Jin Yuhua, et al. A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers. Journal of Semiconductors, 2012, 33(4):045007 doi: 10.1088/1674-4926/33/4/045007
[13]
Chu Xiaojie, Lin Ming, Shi Yin, et al. A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver. Journal of Semiconductors, 2012, 33(3):035004 doi: 10.1088/1674-4926/33/3/035004
Fig. 1.  Charge-pump PLL frequency synthesizer.

Fig. 2.  The bode plot of $\left| {T(s)} \right|$.

Fig. 3.  Block diagram of the multi-standard frequency synthesizer.

Fig. 4.  Complete schematic of the multi-band VCO.

Fig. 5.  Simulated $C$-$V$ characteristics and Δ$C_{\rm eff}$$A$ of the distributed varactor.

Fig. 6.  Programmable integer/fractional frequency divider.

Fig. 7.  Block diagram of MASH 1-1-1.

Fig. 8.  EFM structure of each stage.

Fig. 9.  Circuit implementation of the MASH 1-1-1.

Fig. 10.  Schematic of the divider-by-two circuit.

Fig. 11.  Schematic of PFD, CP, and the third-order loop filter.

Fig. 12.  Chip photo of the frequency synthesizer.

Fig. 13.  Measured tuning characteristic of the VCO.

Fig. 14.  Phase noise measurement results.

Fig. 15.  Measured reference spurs.

Fig. 16.  Measured fractional spurs.

Fig. 17.  Measured locking process in fractional mode and integer mode.

Table 1.   Specifications for the multi-standard frequency synthesizer.

Table 2.   Summary of the measurement results.

Table 3.   Performance comparison with other published works.

[1]
Sand S, Mensing C, Ancha S, et al. Communications and GNSS based navigation:a comparison of current and future trends. Mobile and Wireless Communications Summit, 2007:1 http://ieeexplore.ieee.org/document/4299058/keywords
[2]
Jo J G, Lee J H, Park D J, et al. A L1-band dual-mode RF receiver for GPS and Galileo in 0.18μm CMOS. Radio Frequency Integrated Circuits Symposium, RFIC, 2008:21 https://zh.scribd.com/doc/173018586/Fiber-Optics-Illustrated-Dictionary
[3]
Lu L, Chen J, Yuan L, et al. An 18 mW 1.175-2 GHz frequency synthesizer with constant bandwidth for DVB-T tuners. IEEE Trans Microw Theory Tech, 2009, 57(4):928 doi: 10.1109/TMTT.2009.2014449
[4]
Song J, Park I C. Spur-free MASH delta-Sigma modulation. IEEE Trans Circuits Syst I:Regular Papers, 2010, 57(9):2426 doi: 10.1109/TCSI.2010.2043993
[5]
Yao C Y, Hsieh C C. Hardware simplification to the delta path in a MASH 111 delta sigma modulator. IEEE Trans Circuits Syst Ⅱ:Express Briefs, 2009, 56(4):270 doi: 10.1109/TCSII.2009.2015387
[6]
Hegazi E, Sjoland H, Abidi A A. A filtering technique to lower LC oscillator phase noise. IEEE J Solid-State Circuits, 2001, 36(12):1921 doi: 10.1109/4.972142
[7]
Hegazi E, Abidi A A. Varactor characteristics, oscillator tuning curves, and AM-FM conversion. IEEE J Solid-State Circuits, 2003, 38(6):1033 doi: 10.1109/JSSC.2003.811968
[8]
Mira J, Divel T, Ramet S, et al. Distributed MOS varactor biasing for VCO gain equalization in 0.13μm CMOS technology. Radio Frequency Integrated Circuits Symposium, RFIC, 2004:131 https://zh.scribd.com/document/145600695/RE-1985-11
[9]
Hwang I C, Baek D. A 0.93 mA spur-enhanced frequency synthesizer for L1/L5 dual-band GPS/Galileo RF receiver. IEEE Microw Wireless Compon Lett, 2010, 20(6):355 doi: 10.1109/LMWC.2010.2047533
[10]
Xiao Shimao, Yu Yunfeng, Ma Chengyan, et al. A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver. Journal of Semiconductors, 2010, 31(3):035004 doi: 10.1088/1674-4926/31/3/035004
[11]
Zhou Chunyuan, Li Guoling, Zhang Chun, et al. A fractional-N frequency synthesizer for WCDMA/Bluetooth/ZigBee applications. Journal of Semiconductors, 2009, 30(7):075008 doi: 10.1088/1674-4926/30/7/075008
[12]
Yin Xizhen, Xiao Shimao, Jin Yuhua, et al. A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers. Journal of Semiconductors, 2012, 33(4):045007 doi: 10.1088/1674-4926/33/4/045007
[13]
Chu Xiaojie, Lin Ming, Shi Yin, et al. A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver. Journal of Semiconductors, 2012, 33(3):035004 doi: 10.1088/1674-4926/33/3/035004
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    Received: 16 June 2012 Revised: 10 July 2012 Online: Published: 01 January 2013

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      Bin Li, Xiangning Fan, Wei Li, Li Zhang, Zhigong Wang. A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability[J]. Journal of Semiconductors, 2013, 34(1): 015002. doi: 10.1088/1674-4926/34/1/015002 B Li, X N Fan, W Li, L Zhang, Z G Wang. A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability[J]. J. Semicond., 2013, 34(1): 015002. doi: 10.1088/1674-4926/34/1/015002.Export: BibTex EndNote
      Citation:
      Bin Li, Xiangning Fan, Wei Li, Li Zhang, Zhigong Wang. A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability[J]. Journal of Semiconductors, 2013, 34(1): 015002. doi: 10.1088/1674-4926/34/1/015002

      B Li, X N Fan, W Li, L Zhang, Z G Wang. A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability[J]. J. Semicond., 2013, 34(1): 015002. doi: 10.1088/1674-4926/34/1/015002.
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      A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability

      doi: 10.1088/1674-4926/34/1/015002
      Funds:

      the National Science and Technology Major Project, China 2010ZX03007-002-01

      Project supported by the National Science and Technology Major Project, China (No. 2010ZX03007-002-01) and the State Key Development Program for Basic Research of China (No. 2010CB327404)

      the State Key Development Program for Basic Research of China 2010CB327404

      More Information
      • Corresponding author: Fan Xiangning, xnfan@seu.edu.cn
      • Received Date: 2012-06-16
      • Revised Date: 2012-07-10
      • Published Date: 2013-01-01

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