SEMICONDUCTOR DEVICES

Stability performance of optimized symmetric DG-MOSFET

K Sivasankaran and P S Mallick

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 Corresponding author: P S Mallick, psmallick@vit.ac.in

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Abstract: This article presents the bias and geometry optimization procedure for the radio frequency (RF) stability performance of nanoscale symmetric double-gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs). The stability model can provide hints for optimizing the DG-MOSFET under an RF range. The device parameters are extracted for different bias and geometry conditions through numerical simulation, and the RF figures of merit such as cut-off frequency (ft) and maximum oscillation frequency (fmax), along with stability factor, are calculated for an optimized structure. The proposed structure exhibits good RF stability performance.

Key words: DG-MOSFETradio frequencystability factornumerical simulation



[1]
Wong H S P. Beyond the conventional transistor. IBM Journal of Research and Development, 2002, 6(2.3):133 https://www.coursehero.com/file/16360364/Beyond-the-Transistor/
[2]
Sorin C, Gacuteéard G, Thierry O, et al. Ultimately thin double-gate SOI MOSFETs. IEEE Trans Electron Devices, 2003, 50(3):830 doi: 10.1109/TED.2003.811371
[3]
Liang J, Xiao H, Huang R, et al. Design optimization of structural parameters in double gate MOSFETs for RF application. Semicond Sci Technol, 2008, 23(5):1 doi: 10.1007%2F978-3-642-19542-6_93.pdf
[4]
Mohankumar N, Syamal B, Sarkar C K. Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans Electron Devices, 2010, 57(4):820 doi: 10.1109/TED.2010.2040662
[5]
Sharma R K, Gupta M, Gupta R S. TCAD assessment of device design technologies for enhanced performance of nanoscale DG MOSFET. IEEE Trans Electron Devices, 2011, 58(9):2936 doi: 10.1109/TED.2011.2160065
[6]
Sivasankaran K, Kannadassan D, Seetaram K, et al. Bias and geometry optimization of silicon nanowire transistor:radio frequency stability perspective. Microw Opt Technol Lett, 2012, 54(9):2114 doi: 10.1002/mop.27016
[7]
International Technology Roadmaps for Semiconductor (ITRS), 2005
[8]
Device simulator ATLAS user manual. Silvaco Int. , Santa Clara, CA, May 2006[Online Available]: http://silvaco.com
[9]
Schwierz F, Liou J J. Semiconductor devices for RF applications:evolution and current status. Microelectron Reliab, 2001, 41:145 doi: 10.1016/S0026-2714(00)00076-7
[10]
Gonzales G. Microwave transistor amplifiers——analysis and design. 2nd ed. Prentice-Hall, 1997
[11]
Rollet J M. Stability and power gain invariants of linear two ports. IRE Trans Circuit Theory, 1962, 9:29 doi: 10.1109/TCT.1962.1086854
[12]
Cho S, Kim K R, Park B G, et al. RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs. IEEE Trans Electron Devices, 2011, 58(5):1388 doi: 10.1109/TED.2011.2109724
[13]
Sarkar A, Das A K, De S, et al. Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron J, 2012, 43(11):873 doi: 10.1016/j.mejo.2012.06.002
Fig. 1.  (a) Cross-section view and (b) 3-D schematic view of a symmetric DG-MOSFET

Fig. 2.  The extracted stability factor for different $V_{\rm gs}$ at $V_{\rm ds}$ = 0.8 V

Fig. 3.  The extracted stability factor for different $V_{\rm ds}$ at $V_{\rm gs}$ = 1.2 V

Fig. 4.  Critical frequency as a function of gate voltage

Fig. 5.  The extracted stability factor and $C_{\rm gd}$ for different silicon body thicknesses

Fig. 6.  The extracted stability factor and $C_{\rm gd}$ for different spacer lengths

Fig. 7.  The extracted stability factor for the optimized DG-MOSFET at $V_{\rm gs}$ = 1.2 V and $V_{\rm ds}$ = 0.8 V

Fig. 8.  The variation of $f_{\rm t}$ and $f_{\rm max}$ with drain current for the optimized DG-MOSFET at $V_{\rm gs}$ = 1.2 V and $V_{\rm ds}$ = 0.8 V

[1]
Wong H S P. Beyond the conventional transistor. IBM Journal of Research and Development, 2002, 6(2.3):133 https://www.coursehero.com/file/16360364/Beyond-the-Transistor/
[2]
Sorin C, Gacuteéard G, Thierry O, et al. Ultimately thin double-gate SOI MOSFETs. IEEE Trans Electron Devices, 2003, 50(3):830 doi: 10.1109/TED.2003.811371
[3]
Liang J, Xiao H, Huang R, et al. Design optimization of structural parameters in double gate MOSFETs for RF application. Semicond Sci Technol, 2008, 23(5):1 doi: 10.1007%2F978-3-642-19542-6_93.pdf
[4]
Mohankumar N, Syamal B, Sarkar C K. Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans Electron Devices, 2010, 57(4):820 doi: 10.1109/TED.2010.2040662
[5]
Sharma R K, Gupta M, Gupta R S. TCAD assessment of device design technologies for enhanced performance of nanoscale DG MOSFET. IEEE Trans Electron Devices, 2011, 58(9):2936 doi: 10.1109/TED.2011.2160065
[6]
Sivasankaran K, Kannadassan D, Seetaram K, et al. Bias and geometry optimization of silicon nanowire transistor:radio frequency stability perspective. Microw Opt Technol Lett, 2012, 54(9):2114 doi: 10.1002/mop.27016
[7]
International Technology Roadmaps for Semiconductor (ITRS), 2005
[8]
Device simulator ATLAS user manual. Silvaco Int. , Santa Clara, CA, May 2006[Online Available]: http://silvaco.com
[9]
Schwierz F, Liou J J. Semiconductor devices for RF applications:evolution and current status. Microelectron Reliab, 2001, 41:145 doi: 10.1016/S0026-2714(00)00076-7
[10]
Gonzales G. Microwave transistor amplifiers——analysis and design. 2nd ed. Prentice-Hall, 1997
[11]
Rollet J M. Stability and power gain invariants of linear two ports. IRE Trans Circuit Theory, 1962, 9:29 doi: 10.1109/TCT.1962.1086854
[12]
Cho S, Kim K R, Park B G, et al. RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs. IEEE Trans Electron Devices, 2011, 58(5):1388 doi: 10.1109/TED.2011.2109724
[13]
Sarkar A, Das A K, De S, et al. Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron J, 2012, 43(11):873 doi: 10.1016/j.mejo.2012.06.002
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    Received: 14 March 2013 Revised: 22 April 2013 Online: Published: 01 October 2013

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      K Sivasankaran, P S Mallick. Stability performance of optimized symmetric DG-MOSFET[J]. Journal of Semiconductors, 2013, 34(10): 104001. doi: 10.1088/1674-4926/34/10/104001 K Sivasankaran, P S Mallick. Stability performance of optimized symmetric DG-MOSFET[J]. J. Semicond., 2013, 34(10): 104001. doi: 10.1088/1674-4926/34/10/104001.Export: BibTex EndNote
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      K Sivasankaran, P S Mallick. Stability performance of optimized symmetric DG-MOSFET[J]. Journal of Semiconductors, 2013, 34(10): 104001. doi: 10.1088/1674-4926/34/10/104001

      K Sivasankaran, P S Mallick. Stability performance of optimized symmetric DG-MOSFET[J]. J. Semicond., 2013, 34(10): 104001. doi: 10.1088/1674-4926/34/10/104001.
      Export: BibTex EndNote

      Stability performance of optimized symmetric DG-MOSFET

      doi: 10.1088/1674-4926/34/10/104001
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      • Corresponding author: P S Mallick, psmallick@vit.ac.in
      • Received Date: 2013-03-14
      • Revised Date: 2013-04-22
      • Published Date: 2013-10-01

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