J. Semicond. > 2013, Volume 34 > Issue 3 > 035007, doi: 10.1088/1674-4926/34/3/035007
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SEMICONDUCTOR INTEGRATED CIRCUITS

A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

Qianqian Lei1, , Min Lin2 and Yin Shi2

+ Author Affiliations

 Corresponding author: Lei Qianqian, leiqianqian@163.com

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Abstract: A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with an integrated automatic gain control (AGC) loop for a short-distance receiver are implemented in SMIC 0.13 μm CMOS technology. The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within ±0.5 dB for an input power from -65 to -8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA (I and Q paths) from a 1.2 V supply. Auto LNA gain mode selection with a combined RSSI function is also presented. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.

Key words: limiter, RSSI, AGC, temperature compensation



[1]
Huang P C, Chen Y H, Wang C K. A 2-V 10.7 MHz CMOS limiting amplifier/RSSI. IEEE J Solid-State Circuit, 2000, 35(10):1474 doi: 10.1109/4.871325
[2]
Khorram S, Rofougaran A, Abidi A A. A CMOS limiting amplifier and signal-strength indicator. Symposium on VLSI Circuits Digest of Technical Papers, 1995:95 http://www.ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00520702
[3]
Jindal R P. Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS. IEEE J Solid-State Circuits, 1987, 22:512 doi: 10.1109/JSSC.1987.1052765
[4]
Wu C P, Tsao H W. A 110 MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function. IEEE J Solid-State Circuits, 2005, 40(6):1249 doi: 10.1109/JSSC.2005.848023
[5]
The Y J, Choi Y B, Yeoh W G. A 40 MHz CMOS RSSI with data slicer. ISICIR, 2007:345 http://ieeexplore.ieee.org/iel5/4441779/4441780/04441869.pdf?arnumber=4441869
[6]
Kim H S, Ismail M, Olsson H. CMOS limiters with RSSIs for bluetooth receivers. MWSCAS, 2001:812 http://ieeexplore.ieee.org/document/986311/
[7]
Gregorian R. Introduction to CMOS op-amps and comparators. A Wiley-Interscience Publication, 1999:190 http://cds.cern.ch/record/1541344
[8]
Zhan Chenchang, Wang Wei, Zhou Xiaofang, et al. A new bandgap reference for high-resolution data converters. ICIT, 2007:488 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4290525
[9]
Yang C, Mason A. Process/temperature variation tolerant precision signal strength indicator. IEEE Trans circuits Syst I, 2008, 55(3):722 doi: 10.1109/TCSI.2008.919747
Fig. 1.  Block diagram of a typical wireless receiver.

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Fig. 2.  System block diagram for the RSSI with an AGC loop.

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Fig. 3.  RSSI output performance. (b) LNA gain tuning state diagram.

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Fig. 4.  The simulated AGC loop performance.

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Fig. 5.  Block diagram of the RSSI.

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Fig. 6.  Architecture of the RSSI circuit.

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Fig. 7.  Power consumption versus gain stage number.

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Fig. 8.  Linear error versus number of gain stage.

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Fig. 9.  Schematic of the limiting gain cell.

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Fig. 10.  Schematic of the full wave current rectifier.

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Fig. 11.  Schematic of a comparator with hysteresis.

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Fig. 12.  Hysteresis curve.

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Fig. 13.  Current bias generation circuit.

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Fig. 14.  RSSI performance at different temperatures. (a) Without temperature compensation. (b) With temperature compensation.

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Fig. 15.  RSSI performance at different corners. (a) Without corner compensation. (b) With corner compensation.

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Fig. 16.  Die photograph of the proposed RSSI with an AGC loop.

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Fig. 17.  RSSI output at two different chips.

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Fig. 18.  RSSI output with temperature variation under a compensation circuit.

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Fig. 19.  Measured limiter outputs.

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Fig. 20.  Measured limiter outputs.

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Table 1.   Performances of the proposed limiter and RSSI.

Table 2.   RSSI performance comparison.
[1]
Huang P C, Chen Y H, Wang C K. A 2-V 10.7 MHz CMOS limiting amplifier/RSSI. IEEE J Solid-State Circuit, 2000, 35(10):1474 doi: 10.1109/4.871325
[2]
Khorram S, Rofougaran A, Abidi A A. A CMOS limiting amplifier and signal-strength indicator. Symposium on VLSI Circuits Digest of Technical Papers, 1995:95 http://www.ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00520702
[3]
Jindal R P. Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS. IEEE J Solid-State Circuits, 1987, 22:512 doi: 10.1109/JSSC.1987.1052765
[4]
Wu C P, Tsao H W. A 110 MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function. IEEE J Solid-State Circuits, 2005, 40(6):1249 doi: 10.1109/JSSC.2005.848023
[5]
The Y J, Choi Y B, Yeoh W G. A 40 MHz CMOS RSSI with data slicer. ISICIR, 2007:345 http://ieeexplore.ieee.org/iel5/4441779/4441780/04441869.pdf?arnumber=4441869
[6]
Kim H S, Ismail M, Olsson H. CMOS limiters with RSSIs for bluetooth receivers. MWSCAS, 2001:812 http://ieeexplore.ieee.org/document/986311/
[7]
Gregorian R. Introduction to CMOS op-amps and comparators. A Wiley-Interscience Publication, 1999:190 http://cds.cern.ch/record/1541344
[8]
Zhan Chenchang, Wang Wei, Zhou Xiaofang, et al. A new bandgap reference for high-resolution data converters. ICIT, 2007:488 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4290525
[9]
Yang C, Mason A. Process/temperature variation tolerant precision signal strength indicator. IEEE Trans circuits Syst I, 2008, 55(3):722 doi: 10.1109/TCSI.2008.919747

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    Received: 18 July 2012 Revised: 24 August 2012 Online: Published: 01 March 2013

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      Article Navigation >  Journal of Semiconductors  > 2013  >  34(3): 035007
      Qianqian Lei, Min Lin, Yin Shi. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop[J]. Journal of Semiconductors, 2013, 34(3): 035007. doi: 10.1088/1674-4926/34/3/035007 Q Q Lei, M Lin, Y Shi. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop[J]. J. Semicond., 2013, 34(3): 035007. doi: 10.1088/1674-4926/34/3/035007.Export: BibTex EndNote
      Citation:
      Qianqian Lei, Min Lin, Yin Shi. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop[J]. Journal of Semiconductors, 2013, 34(3): 035007. doi: 10.1088/1674-4926/34/3/035007

      Q Q Lei, M Lin, Y Shi. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop[J]. J. Semicond., 2013, 34(3): 035007. doi: 10.1088/1674-4926/34/3/035007.
      Export: BibTex EndNote
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      A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

      doi: 10.1088/1674-4926/34/3/035007
      • 1.

        Department of Physics, Xi'an Polytechnic University, Xi'an 710048, China

      • 2.

        Suzhou-CAS Semiconductors Integrated Technology Research Center, Suzhou 215021, China

      Funds:

      Project supported by the Doctoral Scientific Starting Research from the Xi'an Polytechnic University, China, and the Doctoral Scientific Starting Research from the Xi'an Polytechnic University (No. BS1209)

      the Doctoral Scientific Starting Research from the Xi'an Polytechnic University BS1209

      the Doctoral Scientific Starting Research from the Xi'an Polytechnic University, China 

      More Information
      • Corresponding author: Lei Qianqian, leiqianqian@163.com
      • Received Date: 2012-07-18
      • Revised Date: 2012-08-24
      • Published Date: 2013-03-01

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