Fig. 1.
Cross-section view of the geometry of the SWCNT bundle interconnects
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Libo Qian, Zhangming Zhu, Ruixue Ding, Yintang Yang. Circuit modeling and performance analysis of SWCNT bundle 3D interconnects[J]. Journal of Semiconductors, 2013, 34(9): 095014. doi: 10.1088/1674-4926/34/9/095014
L B Qian, Z M Zhu, R X Ding, Y T Yang. Circuit modeling and performance analysis of SWCNT bundle 3D interconnects[J]. J. Semicond., 2013, 34(9): 095014. doi: 10.1088/1674-4926/34/9/095014.
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Circuit modeling and performance analysis of SWCNT bundle 3D interconnects
doi: 10.1088/1674-4926/34/9/095014
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Abstract
Metallic carbon nanotubes (CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits (ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube (SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional (3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively. -
References
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